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t echnical manual cmos 4 - bit single chip microcomputer s1c60n02 technical hardware s1c60n02
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revisions and additions for this manual section appendix b appendix c page 88 91 item a/d converter error factors ratings external dimension contents figure b.4 and the explanation were added. the table was revised. the figure was revised. chapter appendices

s 1 c 6 0 / 6 2 f a m i l y d e v i c e s s 1 c 6 0 n 0 1 f 0 a 0 1 p a c k i n g s p e c i f i c a t i o n s 0 0 : b e s i d e s t a p e & r e e l 0 a : t c p b l 2 d i r e c t i o n s 0 b : t a p e & r e e l b a c k 0 c : t c p b r 2 d i r e c t i o n s 0 d : t c p b t 2 d i r e c t i o n s 0 e : t c p b d 2 d i r e c t i o n s 0 f : t a p e & r e e l f r o n t 0 g : t c p b t 4 d i r e c t i o n s 0 h : t c p b d 4 d i r e c t i o n s 0 j : t c p s l 2 d i r e c t i o n s 0 k : t c p s r 2 d i r e c t i o n s 0 l : t a p e & r e e l l e f t 0 m : t c p s t 2 d i r e c t i o n s 0 n : t c p s d 2 d i r e c t i o n s 0 p : t c p s t 4 d i r e c t i o n s 0 q : t c p s d 4 d i r e c t i o n s 0 r : t a p e & r e e l r i g h t 9 9 : s p e c s n o t f i x e d s p e c i f i c a t i o n p a c k a g e d : d i e f o r m ; f : q f p m o d e l n u m b e r m o d e l n a m e c : m i c r o c o m p u t e r , d i g i t a l p r o d u c t s p r o d u c t c l a s s i f i c a t i o n s 1 : s e m i c o n d u c t o r d e v e l o p m e n t t o o l s s 5 u 1 c 6 0 r 0 8 d 1 1 p a c k i n g s p e c i f i c a t i o n s 0 0 : s t a n d a r d p a c k i n g v e r s i o n 1 : v e r s i o n 1 t o o l t y p e h x : i c e e x : e v a b o a r d p x : p e r i p h e r a l b o a r d w x : f l a s h r o m w r i t e r f o r t h e m i c r o c o m p u t e r x x : r o m w r i t e r p e r i p h e r a l b o a r d c x : c c o m p i l e r p a c k a g e a x : a s s e m b l e r p a c k a g e d x : u t i l i t y t o o l b y t h e m o d e l q x : s o f t s i m u l a t o r c o r r e s p o n d i n g m o d e l n u m b e r 6 0 r 0 8 : f o r s 1 c 6 0 r 0 8 t o o l c l a s s i f i c a t i o n c : m i c r o c o m p u t e r u s e p r o d u c t c l a s s i f i c a t i o n s 5 u 1 : d e v e l o p m e n t t o o l f o r s e m i c o n d u c t o r p r o d u c t s 0 0 0 0 c o n f i g u r a t i o n o f p r o d u c t n u m b e r

s1c60n02 technical manual epson i contents contents chapter 1 introduction ................................................................ 1 1.1 configuration .................................................................... 1 1.2 features ........................................................................... 2 1.3 block diagram .................................................................. 3 1.4 pin layout diagram .......................................................... 4 1.5 pin description ................................................................. 5 chapter 2 power supply and initial reset ................................. 6 2.1 power supply ................................................................... 6 2.2 initial reset ....................................................................... 8 oscillation detection circuit ....................................... 9 reset pin (reset) ..................................................... 9 simultaneous high input to input ports (k00?03) .... 9 internal register following initialization ..................... 10 2.3 test pin (test) ............................................................... 10 chapter 3 cpu, rom, ram ............................................................. 11 3.1 cpu ................................................................................. 11 3.2 rom ................................................................................ 12 3.3 ram ................................................................................ 12 chapter 4 peripheral circuits and operation ....................... 13 4.1 memory map ................................................................... 13 4.2 oscillation circuit ............................................................. 16 crystal oscillation circuit .......................................... 16 cr oscillation circuit ................................................ 17
ii epson s1c60n02 technical manual contents 4.3 input ports (k00?03) ..................................................... 18 configuration of input ports ..................................... 18 input comparison registers and interrupt function ... 19 mask option ............................................................. 20 control of input ports ............................................... 20 4.4 output ports (r00?03) .................................................. 22 configuration of output ports ................................... 22 mask option ............................................................. 23 control of output ports ............................................. 25 4.5 i/o ports (p00?03) ........................................................ 28 configuration of i/o ports ........................................ 28 i/o control register and i/o mode ............................ 28 mask option ............................................................. 29 control of i/o ports ................................................. 29 4.6 lcd driver (com0?om3, seg0?eg19) ................... 31 configuration of lcd driver ...................................... 31 cadence adjustment of oscillation frequency ............ 37 mask option (segment allocation) .............................. 38 control of lcd driver ............................................... 40 4.7 clock timer ..................................................................... 41 configuration of clock timer ..................................... 41 interrupt function .................................................... 42 control of clock timer ............................................... 43 4.8 a/d converter .................................................................. 45 configuration of a/d converter ................................ 45 operation of a/d converter ...................................... 46 interrupt function .................................................... 51 usage example of the a/d converter ......................... 51 control of a/d converter .......................................... 53 4.9 heavy load protection function ..................................... 57 operation of heavy load protection function ............. 57 control of heavy load protection function ................. 58 4.10 interrupt and halt .......................................................... 59 interrupt factors ....................................................... 60 specific masks and factor flags for interrupt ............. 61 interrupt vectors ...................................................... 61 control of interrupt .................................................. 62
s1c60n02 technical manual epson iii contents chapter 5 basic external wiring diagram ............................. 63 chapter 6 electrical characteristics ..................................... 65 6.1 absolute maximum rating .............................................. 65 6.2 recommended operating conditions ............................. 66 6.3 dc characteristics .......................................................... 67 6.4 analog circuit characteristics and power current consumption .................................... 69 6.5 oscillation characteristics ............................................... 73 chapter 7 package ....................................................................... 75 7.1 plastic package ............................................................... 75 7.2 ceramic package for test samples ................................ 76 chapter 8 pad layout ................................................................... 77 8.1 diagram of pad layout .................................................... 77 8.2 pad coordinates .............................................................. 78 appendices technical information ............................................ 79 appendix a design steps for designing thermometer ...................... 79 thermometer design steps ........................................ 79 how to obtain capacitor value and oscillation frequency .. 81 setting up counter initial value ................................ 82 computation method of displayed temperature by linear approximation ........................................... 83 appendix b error factors ................................................................... 85 thermistor resistance dispersion .............................. 85 a/d converter error factors ...................................... 85 error by floating capacity ......................................... 89 software error .......................................................... 89 appendix c at thermistor .................................................................. 90

s1c60n02 technical manual epson 1 chapter 1: introduction chapter 1 1.1 table 1.1.1 configuration of the s1c60n02 series introduction each member of the s1c60n02 series of single chip micro- computers feature a 4-bit s1c6200b core cpu, 1,024 words of rom (12 bits per word), 80 words of ram (4 bits per word), an lcd driver, 4 bits for input ports (k00?03), 4 bits for output ports (r00?03), one 4-bit i/o port (p00 p03), clock timer and a/d converter. because of their low voltage operation and low power con- sumption, the s1c60n02 series are ideal for a wide range of applications. configuration the s1c60n02 series are configured as follows, depending on the supply voltage. model supply voltage oscillation circuits 1.8?.5 v 1.2?.0 v s1c60n02 s1c60l02 crystal or cr crystal or cr
2 epson s1c60n02 technical manual chapter 1: introduction features crystal or cr oscillation circuit, 32,768 hz (typ.) 100 instructions 1,024 words 12 bits 80 words 4 bits 4 bits (supplementary pull-down resistors may be used) 4 bits (piezo buzzer and programmable frequency output can be driven directry by mask option) 4 bits 20 segments 4 common duty (or 3 and 2 common duty) clock timer cr oscillation type a/d converter built-in input port interrupt 1 system timer interrupt 1 system a/d converter interrupt 1 system 1.5 v (1.2?.0 v) s1c60l02 (during a/d conversion) 3.0 v (1.8?.5 v) s1c60n02 1.0 ? (crystal oscillation clk = 32,768 hz, when halted) 2.5 ? (crystal oscillation clk = 32,768 hz, when executing) qfp6-60pin (plastic) or chip 1.2 built-in oscillation circuit instruction set rom capacity ram capacity (data ram) input port output port input/output port lcd driver timer a/d converter interrupts: external interrupt internal interrupt supply voltage current consumption (typ.) supply form
s1c60n02 technical manual epson 3 chapter 1: introduction v dd v l1? ca?b v s1 v ss com0? seg0?9 k00?3 p00?3 r00?3 osc1 osc2 reset test power controller ram 80 words x 4 bits rom 1,024 words x 12 bits osc system reset control fout & buzzer interrupt generator input port test port lcd driver i/o port output port timer a/d converter core cpu s1c6200b fout / buzzer buzzer adout rs th cs 1.3 fig. 1.3.1 block diagram block diagram
4 epson s1c60n02 technical manual chapter 1: introduction 31 45 16 30 index 15 1 60 46 1.4 qfp6-60pin pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pin no. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 pin name n.c. test reset seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 com0 com1 com2 com3 pin no. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 pin name n.c. v l3 v l2 v l1 ca cb v ss v dd osc1 osc2 v s1 p00 p01 p02 p03 pin no. 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 pin name seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 n.c. n.c. n.c. pin name n.c. k00 k01 k02 k03 r00 r01 r02 r03 rs th cs adout n.c. n.c. pin layout diagram fig. 1.4.1 pin assignment n.c. = no connection
s1c60n02 technical manual epson 5 chapter 1: introduction 1.5 table 1.5.1 pin description terminal name v dd v ss v s1 v l1 v l2 v l3 ca, cb osc1 osc2 k00 k03 p00 p03 r00 r03 seg0 19 com0 3 cs rs th adout reset test pin no. 38 37 41 34 33 32 35, 36 39 40 47 50 42 45 51 54 1 12 19 26 27 30 57 55 56 58 18 17 input/output (i) (i) o o o o i o i i/o o o o i o o o i i function power source (+) terminal power source (-) terminal oscillation and internal logic system regulated voltage output terminal lcd system regulated voltage output terminal lcd system booster output terminal lcd system booster output terminal booster capacitor connecting terminal crystal or cr oscillation input terminal crystal or cr oscillation output terminal input terminal i/o terminal output terminal lcd segment output terminal (convertible to dc output terminal by mask option) lcd common output terminal a/d converter cr oscillation input terminal a/d converter cr oscillation output terminal a/d converter cr oscillation output terminal a/d converter oscillation frequency output terminal initial setting input terminal test input terminal pin description
6 epson s1c60n02 technical manual chapter 2: power supply and initial reset power supply and initial reset chapter 2 2.1 note power supply with a single external power supply ( * 1) supplied to v dd through v ss , the s1c60n02 series generate the necessary internal voltages with the regulated voltage circuit ( for oscillators and internal circuit) and the voltage booster/ reducer ( for lcds). when the s1c60n02 lcd power is selected for 4.5 v lcd panel by mask option, the s1c60n02 short-circuits between and in internally, and the voltage booster/ reducer generates and . when 3.0 v lcd panel is selected, the s1c60n02 short-circuits between and , and the voltage reducer generates and . the s1c60l02 short-circuits between and , and the voltage booster generates and . the voltage for the internal circuit that is generated by the regulated voltage circuit is -1.2 v (v dd standard). figure 2.1.1 shows the power supply configuration of the s1c60n02 series in each condition. * 1 supply voltage: s1c60n02 .... 3.0 v s1c60l02 .... 1.5 v - external loads cannot be driven by the output voltage of the regulated voltage circuit and the voltage booster/reducer. - see chapter 6, "electrical characteristics", for voltage values.
s1c60n02 technical manual epson 7 chapter 2: power supply and initial reset ?s1c60n02 4.5 v lcd panel 1/4, 1/3, 1/2 duty, 1/3 bias note: v l2 is shorted to v ss inside the ic. 3 v lcd panel 3 v lcd panel 1/4, 1/3, 1/2 duty, 1/3 bias 1/4, 1/3, 1/2 duty, 1/2 bias ?s1c60l02 4.5 v lcd panel 3 v lcd panel 1/4, 1/3, 1/2 duty, 1/3 bias 1/4, 1/3, 1/2 duty, 1/2 bias note: v l1 is shorted to v ss inside the ic. fig. 2.1.1 external element configuration of power system note: v l3 is shorted to v ss inside the ic. v dd v s1 v l1 v l2 v l3 ca cb v ss 3 v c 2 c 3 c 5 c 1 v dd v s1 v l1 v l2 v l3 ca cb v ss 3 v c 2 c 3 c 4 c 1 v dd v s1 v l1 v l2 v l3 ca cb v ss 3 v c 2 c 3 c 1 v dd v s1 v l1 v l2 v l3 ca cb v ss 1.5 v c 2 c 4 c 5 c 1 v dd v s1 v l1 v l2 v l3 ca cb v ss 1.5 v c 2 c 5 c 1
8 epson s1c60n02 technical manual chapter 2: power supply and initial reset initial reset to initialize the s1c60n02 series circuits, an initial reset must be executed. there are three ways of doing this. (1) initial reset by the oscillation detection circuit ( note ) (2) external initial reset via the reset pin (3) external initial reset by simultaneous high input to pins k00?03 (depending on mask option) figure 2.2.1 shows the configuration of the initial reset circuit. 2.2 vss reset k03 k02 k01 k00 osc2 osc1 osc1 oscillation circuit vss oscillation detection circuit noise rejection circuit initial reset noise rejection circuit fig. 2.2.1 configuration of initial reset circuit since the circuit may sometimes not operate normally with the initial resetting by the oscillation detection circuit indicated in number (1), depending on the method of making the power, you should utilize one of the initial resetting methods mentioned in numbers (2) and (3). note
s1c60n02 technical manual epson 9 chapter 2: power supply and initial reset when the oscillation circuit has been stopped until the oscillation circuit begins to oscillate when the power is turned on or for any other reason, the oscillation detection circuit will output an initial reset signal, but since the circuit may sometimes not operate normally with the initial resetting due to the oscillation detection circuit, depending on the method of making the power, you should utilize one of the initial resetting methods indicated hereafter. an initial reset can be invoked externally by making the reset pin high. this high level must be maintained for at least 5 ms (when oscillating frequency, fosc = 32 khz), because the initial reset circuit contains a noise rejection circuit. when the reset pin goes low the cpu begins to operate. another way of invoking an initial reset externally is to input a high signal simultaneously to the input ports (k00?03) selected with the mask option. the specified input port pins must be kept high for at least 4 sec (when oscillating fre- quency fosc = 32 khz), because of the noise rejection circuit. table 2.2.1 shows the combinations of input ports (k00 k03) that can be selected with the mask option. a not used b k00*k01 c k00*k01*k02 d k00*k01*k02*k03 when, for instance, mask option d (k00 * k01 * k02 * k03) is selected, an initial reset is executed when the signals input to the four ports k00?03 are all high at the same time. if you use this function, make sure that the specified ports do not go high at the same time during normal operation. oscillation detection circuit reset pin (reset) table 2.2.1 input port combinations simultaneous high input to input ports (k00?03)
10 epson s1c60n02 technical manual chapter 2: power supply and initial reset internal register fol- lowing initialization an initial reset initializes the cpu as shown in the table below. cpu core name program counter step program counter page new page pointer stack pointer index register x index register y register pointer general register a general register b interrupt flag decimal flag zero flag carry flag signal pcs pcp npp sp x y rp a b i d z c number of bits 8 4 4 8 8 8 4 4 4 1 1 1 1 setting value 00h 1h 1h undefined undefined undefined undefined undefined undefined 0 0 undefined undefined table 2.2.2 initial values 2.3 peripheral circuits name ram display memory other peripheral circuit number of bits 80 4 20 4 setting value undefined undefined *1 * 1: see section 4.1, "memory map" test pin (test) this pin is used when ic is inspected for shipment. during normal operation connect it to v ss .
s1c60n02 technical manual epson 11 chapter 3: cpu, rom, ram cpu, rom, ram cpu the s1c60n02 series employs the s1c6200b core cpu, so that register configuration, instructions, and so forth are virtually identical to those in other processors in the family using the s1c6200b. refer to the "s1c6200/6200a core cpu manual" for details of the s1c6200b. note the following points with regard to the s1c60n02 series: (1) the sleep operation is not provided, so the slp instruc- tion cannot be used. (2) because the rom capacity is 1,024 words, 12 bits per word, bank bits are unnecessary, and pcb and nbp are not used. (3) the ram page is set to 0 only, so the page part (xp, yp) of the index register that specifies addresses is invalid. push xp push yp pop xp pop yp ld xp,r ld yp,r ld r,xp ld r,yp chapter 3 3.1
12 epson s1c60n02 technical manual chapter 3: cpu, rom, ram rom the built-in rom, a mask rom for the program, has a capacity of 1,024 12-bit steps. the program area is 4 pages (0?), each consisting of 256 steps (00h?fh). after an initial reset, the program start address is page 1, step 00h. the interrupt vector is allocated to page l, steps 01h 07h. 3.2 ram the ram, a data memory for storing a variety of data, has a capacity of 80 words, 4-bit words. when programming, keep the following points in mind: (1) part of the data memory is used as stack area when saving subroutine return addresses and registers, so be careful not to overlap the data area and stack area. (2) subroutine calls and interrupts take up three words on the stack. (3) data memory 000h?0fh is the memory area pointed by the register pointer (rp). 3.3 fig. 3.2.1 rom configuration 00h step 07h step 08h step ffh step 12 bits program start address interrupt vector area bank 0 program area 0 page 1 page 2 page 3 page 01h step
s1c60n02 technical manual epson 13 chapter 4: peripheral circuits and operation (memory map) peripheral circuits and operation peripheral circuits (timer, i/o, and so on) of the s1c60n02 series are memory mapped. thus, all the peripheral circuits can be controlled by using memory operations to access the i/o memory. the following sections describe how the pe- ripheral circuits operate. chapter 4 memory map the data memory of the s1c60n02 series has an address space of 154 words, of which 32 words are allocated to display memory and 26 words, to i/o memory. figure 4.1.1 show the overall memory map for the s1c60n02 series, and tables 4.1.1(a) and (b), the memory maps for the peripheral circuits (i/o space). 4.1 address page high low 0123456789abcde f m0 m1 m2 m3 m4 m5 m6 m7 m8 m9 ma mb mc md me mf 3 0 1 2 4 5 6 7 8 9 a b c d e f 0 ram area (000h?4fh) 80 words x 4 bits (r/w) display memory area (090h?afh) 32 words x 4 bits (write only) unused area i/o memory area table 4.1.1(a), (b) fig. 4.1.1 memory map note memory is not mounted in unused area within the memory map and in memory area not indicated in this chapter. for this reason, normal operation cannot be assured for programs that have been prepared with access to these areas.
14 epson s1c60n02 technical manual chapter 4: peripheral circuits and operation (memory map) table 4.1.1(a) i/o memory map * 1 initial value following initial reset * 2 not set in the circuit * 3 undefined * 4 reset (0) immediately after being read * 5 always "0" when being read * 6 refer to main manual address comment register d3 d2 d1 d0 name init 1 0 *1 0e0h k00 r k03 k02 k01 k00 input port data k03 input port data k02 input port data k01 input port data k00 high high high high low low low low k01 k02 k03 *2 *2 *2 *2 0e3h tm0 r tm3 tm2 tm1 tm0 clock timer data 2 hz clock timer data 4 hz clock timer data 8 hz clock timer data 16 hz high high high high low low low low tm1 tm2 tm3 *3 *3 *3 *3 0e4h tc0 r/w tc3 tc2 tc1 tc0 up/down counter data tc3 up/down counter data tc2 up/down counter data tc1 up/down counter data tc0 (lsb) 1 1 1 1 0 0 0 0 tc1 tc2 tc3 *3 *3 *3 *3 tc4 r/w tc7 tc6 tc5 tc4 up/down counter data tc7 up/down counter data tc6 up/down counter data tc5 up/down counter data tc4 1 1 1 1 0 0 0 0 tc5 tc6 tc7 0e5h *3 *3 *3 *3 0e6h tc8 r/w tc11 tc10 tc9 tc8 up/down counter data tc11 up/down counter data tc10 up/down counter data tc9 up/down counter data tc8 1 1 1 1 0 0 0 0 tc9 tc10 tc11 *3 *3 *3 *3 0e7h tc12 r/w tc15 tc14 tc13 tc12 up/down counter data tc15 (msb) up/down counter data tc14 up/down counter data tc13 up/down counter data tc12 1 1 1 1 0 0 0 0 tc13 tc14 tc15 *3 *3 *3 *3 0e8h eik00 r/w eik03 eik02 eik01 eik00 0 0 0 0 interrupt mask register k03 interrupt mask register k02 interrupt mask register k01 interrupt mask register k00 enable enable enable enable mask mask mask mask eik01 eik02 eik03 0ebh eit32 0 eit2 eit8 eit32 0 0 0 interrupt mask register (clock timer) 2 hz interrupt mask register (clock timer) 8 hz interrupt mask register (clock timer) 32 hz enable enable enable mask mask mask eit8 r/w eit2 0 r *5 0ech eiad r/w 0 0 0 eiad 0 interrupt mask register (a/d) enable mask 0 0 r 0 *5 *5 *5 0efh it32 r 0 it2 it8 it32 0 0 0 interrupt factor flag (clock timer) 2 hz interrupt factor flag (clock timer) 8 hz interrupt factor flag (clock timer) 32 hz yes yes yes no no no it8 it2 0 *5 *4 *4 *4 0edh ik0 0 0 0 ik0 0 interrupt factor flag (k00?03) yes no 0 0 0 *5 *5 *5 *4 r
s1c60n02 technical manual epson 15 chapter 4: peripheral circuits and operation (memory map) table 4.1.1(b) i/o memory map address comment register d3 d2 d1 d0 name init 1 0 *1 0f4h p00 r/w p03 p02 p01 p00 i/o port data p03 i/o port data p02 i/o port data p01 i/o port data p00 high high high high low low low low p01 p02 p03 *2 *2 *2 *2 0f5h c0 r/w c3 c2 c1 c0 up-counter data c3 up-counter data c2 up-counter data c1 up-counter data c0 (lsb) 1 1 1 1 0 0 0 0 c1 c2 c3 *3 *3 *3 *3 c4 r/w c7 c6 c5 c4 up-counter data c7 up-counter data c6 up-counter data c5 up-counter data c4 1 1 1 1 0 0 0 0 c5 c6 c7 0f6h *3 *3 *3 *3 0f7h c8 r/w c11 c10 c9 c8 up-counter data c11 up-counter data c10 up-counter data c9 up-counter data c8 1 1 1 1 0 0 0 0 c9 c10 c11 *3 *3 *3 *3 0f8h c12 r/w c15 c14 c13 c12 up-counter data c15 (msb) up-counter data c14 up-counter data c13 up-counter data c12 1 1 1 1 0 0 0 0 c13 c14 c15 *3 *3 *3 *3 0f9h tmrst w 0 0 0 tmrst reset clock timer reset reset 0 0 r 0 *5 *5 *5 *5 0fbh 0 csdc 0 0 0 0 lcd drive switch static dynamic 0 r 0 csdc r/w *5 *5 *5 0fdh xfout0 r/w xbzr 0 xfout1 xfout0 0 0 0 buzzer frequency control fout frequency control fout frequency control 2 khz 4 khz xfout1 0 r xbzr r/w *5 *6 *6 0fch ioc r/w 0 0 0 ioc 0 i/o port i/o control register out in 0 0 r 0 *5 *5 *5 0feh adclk r/w 0 0 0 adclk 0 a/d clock selection 65 khz/32 khz 65 khz 32 khz 0 0 r 0 *5 *5 *5 0f1h adrun r/w 0 0 0 adrun 0 a/d conversion start/stop start stop 0 0 r 0 *5 *5 *5 0f0h iad 0 0 0 iad 0 interrupt factor flag (a/d) yes no 0 0 0 *5 *5 *5 *4 r 0f3h r00 fout r03 r02 r01 buzzer r00 fout 0 0 0 0 0 0 output port data r03 output port data r02 output port data r01 buzzer on/off control register output port data r00 frequency output control register high high high on high on low low low off low off r01 buzzer r02 r03 r/w 0fah 0 hlmod 0 0 0 0 heavy load protection mode register heavy normal 0 0 hlmod r/w *5 *5 *5 r
16 epson s1c60n02 technical manual chapter 4: peripheral circuits and operation (oscillation circuit) oscillation circuit the s1c60n02 series has a built-in oscillation circuit. for the oscillation circuit, eiter crystal oscillation or cr oscillation may be selected by a mask option. the crystal oscillation circuit generates the operating clock for the cpu and peripheral circuit on connection to an external crystal oscillator (typ. 32.768 khz) and trimmer capacitor (5?5 pf). figure 4.2.1 is the block diagram of the crystal oscillation circuit. 4.2 crystal oscillation circuit fig. 4.2.1 crystal oscillation circuit v dd c g x'tal osc2 osc1 r r d c d v dd to cpu and peripheral circuits the s1c60n02 series f as figure 4.2.1 indicates, the crystal oscillation circuit can be configured simply by connecting the crystal oscillator (x'tal) between the osc1 and osc2 pins and the trimmer capacitor (c g ) between the osc1 and v dd pins.
s1c60n02 technical manual epson 17 chapter 4: peripheral circuits and operation (oscillation circuit) for the s1c60n02 series, cr oscillation circuit (typ. 65 khz) may be selected by a mask option. figure 4.2.2 is the block diagram of the cr oscillation circuit. cr oscillation circuit fig. 4.2.2 cr oscillation circuit osc2 osc1 c to cpu and peripheral circuits the s1c60n02 series r cr as figure 4.2.2 indicates, the cr oscillation circuit can be configured simply by connecting the register (r cr ) between pins osc1 and osc2 since capacity (c) is built-in. see chapter 6, "electrical characteristics" for r cr value.
18 epson s1c60n02 technical manual chapter 4: peripheral circuits and operation (input ports) input ports (k00?03) the s1c60n02 series has a general-purpose input (4 bits). each of the input port pins (k00?03) has an internal pull- down resistance. the pull-down resistance can be selected for each bit with the mask option. figure 4.3.1 shows the configuration of input port. kxx v ss mask option address v dd interrupt request data bus selecting "pull-down resistance enabled" with the mask option allows input from a push button, key matrix, and so forth. when "pull-down resistance disabled" is selected, the port can be used for slide switch input and interfacing with other lsis. 4.3 configuration of input ports fig. 4.3.1 configuration of input port
s1c60n02 technical manual epson 19 chapter 4: peripheral circuits and operation (input ports) input comparison registers and inter- rupt function the interrupt mask registers (eik00?ik03) enable the interrupt mask to be selected individually for k00?03. an interrupt occurs when the input value which are not masked change and the interrupt factor flag (ik0) is set to "1". fig. 4.3.2 input interrupt circuit configuration (k00?03) all four input port bits (k00?03) provide the interrupt function. the conditions for issuing an interrupt can be set by the software for the four bits. also, whether to mask the interrupt function can be selected individually for all four bits by the software. figure 4.3.2 shows the configuration of k00?03. data bus address interrupt mask register (eik) kxx address mask option (k00 k03) noise rejector one for each pin series interrupt request address interrupt factor flag (ik)
20 epson s1c60n02 technical manual chapter 4: peripheral circuits and operation (input ports) the contents that can be selected with the input port mask option are as follows: (1) an internal pull-down resistance can be selected for each of the four bits of the input ports (k00?03). having selected "pull-down resistance disabled", take care that the input does not float. select "pull-down resistance enabled" for input ports that are not being used. (2) the input interrupt circuit contains a noise rejection circuit to prevent interrupts form occurring through noise. the mask option enables selection of the noise rejection circuit for each separate pin series. when "use" is selected, a maximum delay of 0.5 ms (fosc = 32 khz) occurs from the time an interrupt condition is established until the interrupt factor flag (ik) is set to "1". table 4.3.1 list the input port control bits and their ad- dresses. mask option control of input ports table 4.3.1 input port control bits * 1 initial value following initial reset * 2 not set in the circuit * 3 undefined * 4 reset (0) immediately after being read * 5 always "0" when being read * 6 refer to main manual address comment register d3 d2 d1 d0 name init 1 0 *1 0e0h k00 r k03 k02 k01 k00 input port data k03 input port data k02 input port data k01 input port data k00 high high high high low low low low k01 k02 k03 *2 *2 *2 *2 0e8h eik00 r/w eik03 eik02 eik01 eik00 0 0 0 0 interrupt mask register k03 interrupt mask register k02 interrupt mask register k01 interrupt mask register k00 enable enable enable enable mask mask mask mask eik01 eik02 eik03 0edh ik0 0 0 0 ik0 0 interrupt factor flag (k00?03) yes no 0 0 0 *5 *5 *5 *4 r
s1c60n02 technical manual epson 21 chapter 4: peripheral circuits and operation (input ports) input port data (0e0h) the input data of the input port pins can be read with these registers. when "1" is read: high level when "0" is read: low level writing: invalid the value read is "1" when the pin voltage of the four bits of the input ports (k00?03) goes high (v dd ), and "0" when the voltage goes low (v ss ). these bits are reading, so writing cannot be done. interrupt mask registers (0e8h) masking the interrupt of the input port pins can be done with these registers. when "1" is written: enable when "0" is written: mask reading: valid with these registers, masking of the input port bits can be done for each of the four bits. after an initial reset, these registers are all set to "0". interrupt factor flags (0edh d0) these flags indicate the occurrence of an input interrupt. when "1" is read: interrupt has occurred when "0" is read: interrupt has not occurred writing: invalid the interrupt factor flag ik0 is associated with k00?03, respectively. from the status of these flags, the software can decide whether an input interrupt has occurred. these flags are reset when the software has read them. reading of interrupt factor flags is available at ei, but be careful in the following cases. if the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. after an initial reset, these flags are set to "0". k00 k03 ik0 eik00 eik03
22 epson s1c60n02 technical manual chapter 4: peripheral circuits and operation (output ports) output ports (r00?03) the s1c60n02 series has 4 bits for general output ports (r00?03). output specifications of the output ports can be selected individually with the mask option. three kinds of output specifications are available: complementary output and pch open drain output. also, the mask option enables the output ports r00 and r01 to be used as special output ports. figure 4.4.1 shows the configuration of the output ports. configuration of output ports 4.4 register data bus address v dd v ss rxx complementary pch open drain mask option fig. 4.4.1 configuration of output ports
s1c60n02 technical manual epson 23 chapter 4: peripheral circuits and operation (output ports) the mask option enables the following output port selection. (1) output specifications of output ports the output specifications for the output ports (r00?03) may be either complementary output or pch open drain output for each of the four bits. however, even when pch open drain output is selected, a voltage exceeding the source voltage must not be applied to the output port. (2) special output in addition to the regular dc output, special output can be selected for output ports r00 and r01, as shown in table 4.4.1. figure 4.4.2 shows the structure of output ports r00?03. mask option table 4.4.1 special output fout or buzzer buzzer r00 r01 pin name when special output is selected fig. 4.4.2 structure of output port r00?03 address (0f3h) fout data bus mask option r02 r01 buzzer register (r03) r03 r00 buzzer register (r02) register (r01) register (r00)
24 epson s1c60n02 technical manual chapter 4: peripheral circuits and operation (output ports) fout (r00) when output port r00 is set for fout output, this port will generate fosc (cpu operating clock frequency) or clock frequency divided into fosc. clock frequency may be se- lected individually for f1?4, from among 5 types by mask option; one among f1?4 is selected by software and used. the types of frequency which may be selected are shown in table 4.4.2. output ports r01 and r00 may be set to buzzer output and buzzer output (buzzer reverse output), respectively, allowing for direct driving of the piezo-electric buzzer. buzzer output (r00) may only be set if r01 is set to buzzer output. in such case, whether on/off of the buzzer output is done through r00 register or is control- led through r01 simultaneously with buzzer output is also selected by mask option. the frequency of buzzer output may be selected by software to be either 2 khz or 4 khz. table 4.4.2 fout clock frequency a hazard may occur when the fout signal is turned on or off. note (d1, d0) = (xfout1, xfout0) setting value clock frequency (hz) 4 256 (fosc/128) 512 (fosc/64) 1,024 (fosc/32) 2,048 (fosc/16) 512 (fosc/64) 1,024 (fosc/32) 2,048 (fosc/16) 8,192 (fosc/4) 1,024 (fosc/32) 2,048 (fosc/16) 4,096 (fosc/8) 4,096 (fosc/8) 8,192 (fosc/4) 16,384 (fosc/2) 4,096 (fosc/8) 32,768 (fosc/1) 2,048 (fosc/16) 4,096 (fosc/8) 8,192 (fosc/4) 16,384 (fosc/2) 1 2 3 5 (d1,d0)=(0,0) (d1,d0)=(0,1) (d1,d0)=(1,0) (d1,d0)=(1,1) f1 f2 f3 f4 fosc = 32,768 buzzer, buzzer (r01, r00)
s1c60n02 technical manual epson 25 chapter 4: peripheral circuits and operation (output ports) output port data (0f3h) sets the output data for the output ports. when "1" is written: high output when "0" is written: low output reading: valid the output port pins output the data written to the corre- sponding registers (r00?03) without changing it. when "1" is written to the register, the output port pin goes high (v dd ), and when "0" is written, the output port pin goes low (v ss ). after an initial reset, all registers are set to "0". r00 r03 table 4.4.3 control bits of output ports control of output ports table 4.4.3 lists the output port control bits and their ad- dresses. * 1 initial value following initial reset * 2 not set in the circuit * 3 undefined * 4 reset (0) immediately after being read * 5 always "0" when being read * 6 refer to main manual address comment register d3 d2 d1 d0 name init 1 0 *1 0f3h r00 fout r03 r02 r01 buzzer r00 fout 0 0 0 0 0 0 output port data r03 output port data r02 output port data r01 buzzer on/off control register output port data r00 frequency output control register high high high on high on low low low off low off r01 buzzer r02 r03 r/w 0fdh xfout0 r/w xbzr 0 xfout1 xfout0 0 0 0 buzzer frequency control fout frequency control fout frequency control 2 khz 4 khz xfout1 0 r xbzr r/w *5 *6 *6
26 epson s1c60n02 technical manual chapter 4: peripheral circuits and operation (output ports) special output port data (0f3h d0) controls the fout (clock) output. when "1" is written: clock output when "0" is written: low level (dc) output reading: valid fout output can be controlled by writing data to r00. after an initial reset, this register is set to "0". figure 4.4.3 shows the output waveform for fout output. r00 (when fout is selected) fig. 4.4.3 fout output waveform fout frequency control (0fdh d0, 0fdh d1) selects the output frequency when r00 port is set for fout output. xfout0, xfout1 table 4.4.4 fout frequency selection 0 0 1 1 xfout1 0 1 0 1 xfout0 f1 f2 f3 f4 frequency selection after an initial reset, these registers are set to "0". r00 register fout output waveform 01
s1c60n02 technical manual epson 27 chapter 4: peripheral circuits and operation (output ports) special output port data (0f3h d0, 0f3h d1) controls the buzzer output. when "1" is written: buzzer output when "0" is written: low level (dc) output reading: valid buzzer and buzzer output can be controlled by writing data to r00 and r01. when buzzer output by r01 register control is selected by mask option, buzzer output and buzzer output can be controlled simultaneously by writing data to r01 register. after an initial reset, these registers are set to "0". figure 4.4.4 shows the output waveform for buzzer output. r00, r01 (when buzzer and buzzer is selected) fig. 4.4.4 buzzer output waveform buzzer frequency control (0fdh d3) selects the frequency of the buzzer signal. when "1" is written: 2 khz when "0" is written: 4 khz reading: valid when r00 and r01 port is set to buzzer output, the fre- quency of the buzzer signal can be selected by this register. when "1" is written to this register, the frequency is set in 2 khz, and in 4 khz when "0" is written. after an initial reset, this register is set to "0". xbzr r01 (r00) register buzzer output waveform 01 buzzer output waveform
28 epson s1c60n02 technical manual chapter 4: peripheral circuits and operation (i/o ports) i/o ports (p00?03) the s1c60n02 series has a 4-bit general-purpose i/o port. figure 4.5.1 shows the configuration of the i/o port. the four bits of the i/o port p00?03 can be set to either input mode or output mode. the mode can be set by writing data to the i/o control register (ioc). 4.5 configuration of i/o ports fig. 4.5.1 configuration of i/o port input or output mode can be set for the four bits of i/o port p00?03 by writing data into i/o control register ioc. to set the input mode, "0" is written to the i/o control register. when an i/o port is set to input mode, its imped- ance becomes high and it works as an input port. however, the input line is pulled down when input data is read. the output mode is set when "1" is written to the i/o control register (ioc). when an i/o port set to output mode works as an output port, it outputs a high signal (v dd ) when the port output data is "1", and a low signal (v ss ) when the port output data is "0". after an initial reset, the i/o control register is set to "0", and the i/o port enters the input mode. i/o control register and i/o mode address register input control i/o control register (ioc) data bus pxx v ss address
s1c60n02 technical manual epson 29 chapter 4: peripheral circuits and operation (i/o ports) the output specification during output mode (ioc = "1") of the i/o port can be set with the mask option for either complementary output or pch open drain output. this setting can be performed for each bit of the i/o port. how- ever, when pch open drain output has been selected, voltage in excess of the supply voltage must not be applied to the port. table 4.5.1 lists the i/o port control bits and their ad- dresses. mask option control of i/o ports table 4.5.1 i/o port control bits i/o port data (0f4h) i/o port data can be read and output data can be written through the port. ?when writing data when "1" is written: high level when "0" is written: low level when an i/o port is set to the output mode, the written data is output from the i/o port pin unchanged. when "1" is written as the port data, the port pin goes high (v dd ), and when "0" is written, the level goes low (v ss ). port data can also be written in the input mode. p00?03 * 1 initial value following initial reset * 2 not set in the circuit * 3 undefined * 4 reset (0) immediately after being read * 5 always "0" when being read * 6 refer to main manual address comment register d3 d2 d1 d0 name init 1 0 *1 0f4h p00 r/w p03 p02 p01 p00 i/o port data p03 i/o port data p02 i/o port data p01 i/o port data p00 high high high high low low low low p01 p02 p03 *2 *2 *2 *2 0fch ioc r/w 0 0 0 ioc 0 i/o port i/o control register out in 0 0 r 0 *5 *5 *5
30 epson s1c60n02 technical manual chapter 4: peripheral circuits and operation (i/o ports) ?when reading data when "1" is read: high level when "0" is read: low level the pin voltage level of the i/o port is read. when the i/ o port is in the input mode the voltage level being input to the port pin can be read; in the output mode the output voltage level can be read. when the pin voltage is high (v dd ) the port data read is "1", and when the pin voltage is low (v ss ) the data is "0". also, the built-in pull- down resistance functions during reading, so the i/o port pin is pulled down. - when the i/o port is set to the output mode and a low-imped- ance load is connected to the port pin, the data written to the register may differ from the data read. - when the i/o port is set to the input mode and a low-level voltage (vss) is input by the built-in pull-down resistance, an erroneous input results if the time constant of the capacitive load of the input line and the built-in pull-down resistance load is greater than the read-out time. when the input data is being read, the time that the input line is pulled down is equivalent to 0.5 cycles of the cpu system clock. hence, the electric poten- tial of the pins must settle within 0.5 cycles. if this condition cannot be met, some measure must be devised, such as arranging a pull-down resistance externally, or performing multiple read-outs. i/o control register (0fch d0) the input or output i/o port mode can be set with this register. when "1" is written: output mode when "0" is written: input mode reading: valid the input or output mode of the i/o port is set in units of four bits. for instance, ioc sets the mode for p00?03. writing "1" to the i/o control register makes the i/o port enter the output mode, and writing "0", the input mode. after an initial reset, the ioc register is set to "0", so the i/o port is in the input mode. note ioc
s1c60n02 technical manual epson 31 chapter 4: peripheral circuits and operation (lcd driver) lcd driver (com0?om3, seg0?eg19) the s1c60n02 series has four common pins and 20 (seg0 seg19) segment pins, so that an lcd with a maximum of 80 (20 4) segments can be driven. the power for driving the lcd is generated by the cpu internal circuit, so there is no need to supply power externally. the driving method is 1/4 duty (or 1/3, 1/2 duty by mask option) dynamic drive, adopting the four types of potential (1/3 bias), v dd , v l1 , v l2 and v l3 . moreover, the 1/2 bias dynamic drive that uses three types of potential, v dd , v l1 = v l2 and v l3 , can be selected by setting the mask option (drive duty can also be selected from 1/4, 1/3 or 1/2). 1/2 bias drive is effective when the lcd system regulated voltage circuit is not used. the v l1 terminal and the v l2 terminal should be connected outside of the ic. the frame frequency is 32 hz for 1/4 duty and 1/2 duty, and 42.7 hz for 1/3 duty (in the case of fosc = 32.768 khz). figure 4.6.1 shows the drive waveform for 1/4 duty (1/3 bias), figure 4.6.2 shows the drive waveform for 1/3 duty (1/3 bias), figure 4.6.3 shows the drive waveform for 1/2 duty (1/3 bias), figure 4.6.4 shows the drive waveform for 1/4 duty (1/2 bias), figure 4.6.5 shows the drive waveform for 1/3 duty (1/2 bias) and figure 4.6.6 shows the drive waveform for 1/2 duty (1/2 bias). fosc indicates the oscillation frequency of the oscillation circuit. configuration of lcd driver 4.6 note
32 epson s1c60n02 technical manual chapter 4: peripheral circuits and operation (lcd driver) fig. 4.6.1 drive waveform for 1/4 duty (1/3 bias) lcd lighting status com0 com1 com2 com3 not lit lit -v dd -v l1 -v l2 -v l3 com0 com1 com2 com3 seg 0?9 frame frequency seg0?9 -v dd -v l1 -v l2 -v l3
s1c60n02 technical manual epson 33 chapter 4: peripheral circuits and operation (lcd driver) fig. 4.6.2 drive waveform for 1/3 duty (1/3 bias) frame frequency seg 0 19 com3 com2 com1 com0 -v dd -v l1 -v l2 -v l3 not lit lit seg0 19 lcd lighting status com0 com1 com2 -v dd -v l1 -v l2 -v l3
34 epson s1c60n02 technical manual chapter 4: peripheral circuits and operation (lcd driver) fig. 4.6.3 drive waveform for 1/2 duty (1/3 bias) com0 com1 com2 com3 seg 0 19 frame frequency -v dd -v l1 -v l2 -v l3 -v dd -v l1 -v l2 -v l3 not lit lit seg0 19 lcd lighting status com0 com1
s1c60n02 technical manual epson 35 chapter 4: peripheral circuits and operation (lcd driver) lcd lighting status not lit lit seg 0 19 seg0 19 frame frequency com0 com1 com2 com3 com0 com1 com2 com3 -v dd -v l1, l2 -v l3 -v dd -v l1, l2 -v l3 fig. 4.6.4 drive waveform for 1/4 duty (1/2 bias)
36 epson s1c60n02 technical manual chapter 4: peripheral circuits and operation (lcd driver) lcd lighting status not lit lit seg 0 19 frame frequency seg0 19 com0 com1 com2 com0 com1 com2 com3 -v dd -v l1, l2 -v l3 -v dd -v l1, l2 -v l3 com0 com1 com0 com1 com2 com3 -v dd -v l1, l2 -v l3 -v dd -v l1, l2 -v l3 lcd lighting status not lit lit seg 0 19 frame frequency seg0 19 fig. 4.6.5 drive waveform for 1/3 duty (1/2 bias) fig. 4.6.6 drive waveform for 1/2 duty (1/2 bias)
s1c60n02 technical manual epson 37 chapter 4: peripheral circuits and operation (lcd driver) cadence adjust- ment of oscillation frequency in the s1c60n02 series, the lcd drive duty can be set to 1/1 duty by software. this function enables easy adjust- ment (cadence adjustment) of the oscillation frequency of the osc circuit. the procedure to set to 1/1 duty drive is as follows: ? write "1" to the csdc register at address "0fbh d3". ? write the same value to all registers corresponding to coms 0 through 3 of the display memory. the frame frequency is 32 hz (f osc1 /1,024, when f osc1 = 32.768 khz). - even when l/3 or 1/2 duty is selected by the mask option, the display data corresponding to all com are valid during 1/1 duty driving. hence, for 1/1 duty drive, set the same value for all display memory corresponding to coms 0 through 3. - for cadence adjustment, set the display data corresponding to coms 0 through 3 , so that all the lcd segments go on. figure 4.6.7 shows the 1/1 duty drive waveform (1/3 bias). figure 4.6.8 shows the 1/1 duty drive waveform (1/2 bias). fig. 4.6.7 1/1 duty drive waveform (1/3 bias) fig. 4.6.8 1/1 duty drive waveform (1/2 bias) note seg 0 19 com 0 3 frame frequency lcd lighting status com0 com1 com2 com3 seg0 19 -v dd -v l1, v l2 -v l3 not lit lit -v dd -v l1, v l2 -v l3 -v dd -v l1, v l2 -v l3 seg 0 19 com 0 3 frame frequency lcd lighting status com0 com1 com2 com3 seg0 19 -v dd -v l1 -v l2 -v l3 -v dd -v l1 -v l2 -v l3 -v dd -v l1 -v l2 -v l3 not lit lit
38 epson s1c60n02 technical manual chapter 4: peripheral circuits and operation (lcd driver) (1) segment allocation as shown in figure 4.l.1, the s1c60n02 series display data is decided by the display data written to the display memory (write-only) at address "090h?afh". the address and bits of the display memory can be made to correspond to the segment pins (seg0?eg19) in any combination through mask option. this simplifies design by increasing the degree of freedom with which the liquid crystal panel can be designed. figure 4.6.9 shows an example of the relationship be- tween the lcd segments (on the panel) and the display memory in the case of 1/3 duty. mask option (segment allocation) fig. 4.6.9 segment allocation aa' f f' g' g ee' d d' p' p c' b' b c seg10 seg11 seg12 common 0 common 1 common 2 09ah 09bh 09ch 09dh address d p d' p' d3 c g c' g' d2 b f b' f' d1 a e a' e' d0 data display data memory allocation seg10 seg11 seg12 9a, d0 (a) 9a, d1 (b) 9d, d1 (f') 9b, d1 (f) 9b, d2 (g) 9a, d2 (c) 9b, d0 (e) 9a, d3 (d) 9b, d3 (p) pin address allocation common 0 common 1 common 2
s1c60n02 technical manual epson 39 chapter 4: peripheral circuits and operation (lcd driver) (2) drive duty according to the mask option, either 1/4, 1/3 or 1/2 duty can be selected as the lcd drive duty. table 4.6.1 shows the differences in the number of seg- ments according to the selected duty. pins used maximum number frame frequency in common of segments (when fosc = 32 khz) 1/4 com0? 80 (20 4) 32 hz 1/3 com0? 60 (20 3) 42.7 hz 1/2 com0? 40 (20 2) 32 hz (3) output specification ? the segment pins (seg0?eg19) are selected by mask option in pairs for either segment signal output or dc output (v dd and v ss binary output). when dc output is selected, the data corresponding to com0 of each segment pin is output. ? when dc output is selected, either complementary output or pch open drain output can be selected for each pin by mask option. the pin pairs are the combination of seg (2 * n) and seg (2 * n + 1) (where n is an integer from 0 to 12). (4) drive bias for the drive bias of the s1c60n02 or the s1c60l02, either 1/3 bias or 1/2 bias can be selected by the mask option. table 4.6.1 differences according to selected duty duty note
40 epson s1c60n02 technical manual chapter 4: peripheral circuits and operation (lcd driver) table 4.6.2 shows the control bits of the lcd driver and their addresses. figure 4.6.10 shows the display memory map. control of lcd driver csdc display memory fig. 4.6.10 display memory map address 0123456789abcde f 090 0a0 display memory (write only) 32 words x 4 bits table 4.6.2 control bits of lcd driver lcd drive switch (0fbh d3) the lcd drive format can be selected with this switch. when "1" is written: static drive when "0" is written: dynamic drive reading: valid after an initial reset, dynamic drive (csdc = "0") is selected. (090h 0afh) the lcd segments are turned on or off according to this data. when "1" is written: on when "0" is written: off reading: invalid by writing data into the display memory allocated to the lcd segment (on the panel), the segment can be turned on or off. after an initial reset, the contents of the display memory are undefined. * 1 initial value following initial reset * 2 not set in the circuit * 3 undefined * 4 reset (0) immediately after being read * 5 always "0" when being read * 6 refer to main manual address comment register d3 d2 d1 d0 name init 1 0 *1 0fbh 0 csdc 0 0 0 0 lcd drive switch static dynamic 0 r 0 csdc r/w *5 *5 *5
s1c60n02 technical manual epson 41 chapter 4: peripheral circuits and operation (clock timer) clock timer the s1c60n02 series has a built-in clock timer driven by the source oscillator. the clock timer is configured as a seven-bit binary counter that serves as a frequency divider taking a 256 hz source clock from a prescaler. the four high-order bits (16 hz? hz) can be read by the software. figure 4.7.1 is the block diagram of the clock timer. 4.7 configuration of clock timer fig. 4.7.1 block diagram of clock timer normally, this clock timer is used for all kinds of timing purpose, such as clocks. 128 hz?2 hz data bus 32 hz, 8 hz, 2 hz 256 hz clock timer reset signal osc (oscillation circuit) interrupt request interrupt control 16 hz? hz
42 epson s1c60n02 technical manual chapter 4: peripheral circuits and operation (clock timer) interrupt function the clock timer can interrupt on the falling edge of the 32 hz, 8 hz, and 2 hz signals. the software can mask any of these interrupt signals. figure 4.7.2 is the timing chart of the clock timer. fig. 4.7.2 timing chart of the clock timer as shown in figure 4.7.2, an interrupt is generated on the falling edge of the 32 hz, 8 hz, and 2 hz frequencies. when this happens, the corresponding interrupt event flag (it32, it8, it2) is set to "1". masking the separate interrupts can be done with the interrupt mask register (eit32, eit8, eit2). however, regardless of the interrupt mask register setting, the interrupt event flags will be set to "1" on the falling edge of their corresponding signal (e.g. the falling edge of the 2 hz signal sets the 2 hz interrupt factor flag to "1"). write to the interrupt mask register (eit32, eit8, eit2) only in the di status (interrupt flag = "0"). otherwise, it causes malfunction. note clock timer timing chart frequency register bits address 0e3h d0 16 hz d1 d2 d3 8 hz 4 hz 2 hz occurrence of 32 hz interrupt request occurrence of 8 hz interrupt request occurrence of 2 hz interrupt request
s1c60n02 technical manual epson 43 chapter 4: peripheral circuits and operation (clock timer) table 4.7.1 shows the clock timer control bits and their addresses. control of clock timer table 4.7.1 control bits of clock timer timer data (0e3h) the l6 hz to 2 hz timer data of the clock timer can be read from this register. these four bits are read-only, and write operations are invalid. after an initial reset, the timer data is initialized to "0h". interrupt mask registers (0ebh d0 d2) these registers are used to mask the clock timer interrupt. when "1" is written: enabled when "0" is written: masked reading: valid the interrupt mask register bits (eit32, eit8, eit2) mask the corresponding interrupt frequencies (32 hz, 8 hz, 2 hz). after an initial reset, these registers are all set to "0". tm0 tm3 eit32, eit8, eit2 * 1 initial value following initial reset * 2 not set in the circuit * 3 undefined * 4 reset (0) immediately after being read * 5 always "0" when being read * 6 refer to main manual address comment register d3 d2 d1 d0 name init 1 0 *1 0e3h tm0 r tm3 tm2 tm1 tm0 clock timer data 2 hz clock timer data 4 hz clock timer data 8 hz clock timer data 16 hz high high high high low low low low tm1 tm2 tm3 *3 *3 *3 *3 0ebh eit32 0 eit2 eit8 eit32 0 0 0 interrupt mask register (clock timer) 2 hz interrupt mask register (clock timer) 8 hz interrupt mask register (clock timer) 32 hz enable enable enable mask mask mask eit8 r/w eit2 0 r *5 0efh it32 r 0 it2 it8 it32 0 0 0 interrupt factor flag (clock timer) 2 hz interrupt factor flag (clock timer) 8 hz interrupt factor flag (clock timer) 32 hz yes yes yes no no no it8 it2 0 *5 *4 *4 *4 0f9h tmrst w 0 0 0 tmrst reset clock timer reset reset 0 0 r 0 *5 *5 *5 *5
44 epson s1c60n02 technical manual chapter 4: peripheral circuits and operation (clock timer) interrupt factor flags (0efh d0 d2) these flags indicate the status of the clock timer interrupt. when "1" is read: interrupt has occurred when "0" is read: interrupt has not occurred writing: invalid the interrupt factor flags (it32, it8, it2) correspond to the clock timer interrupts (32 hz, 8 hz, 2 hz). the software can determine from these flags whether there is a clock timer interrupt. however, even if the interrupt is masked, the flags are set to "1" on the falling edge of the signal. these flags can be reset when the register is read by the software. reading of interrupt factor flags is available at ei, but be careful in the following cases. if the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. be very careful when interrupt factor flags are in the same address. after an initial reset, these flags are set to "0". clock timer reset (0f9h d0) this bit resets the clock timer. when "1" is written: clock timer reset when "0" is written: no operation reading: always "0" the clock timer is reset by writing "1" to tmrst. the clock timer starts immediately after this. no operation results when "0" is written to tmrst. this bit is write-only, and so is always "0" when read. it32, it8, it2 tmrst
s1c60n02 technical manual epson 45 chapter 4: peripheral circuits and operation (a/d converter) configuration of a/d converter 4.8 fig. 4.8.1 configuration of a/d converter a/d converter the s1c60n02 series has a cr oscillation type a/d con- verter. this a/d converter is equipped with two cr oscilla- tion circuit systems and a counter that measures their oscillation frequency. counted values represent connected resistance values converted into digital values. connect a reference resistance that does not change oscillation fre- quency according to temperature between the rs and cs terminals and a sensor that does change resistance values according to temperature between the th and cs terminals. then, oscillate them alternately. the difference in the counted value can be evaluated as the difference between the respective oscillation frequencies. therefore, various sensor circuit such as a temperature-measuring circuit using a thermistor can be easily created, for example. the configuration of the a/d converter is shown in figure 4.8.1. tr2 multiplying circuit interrupt request osc1 clock 32 khz or 65 khz tc15 ?c12 tc11 ?c8 tc7 ?c4 tc3 ?c0 up/down counter adclk c15 ?12 c11 ?8 c7 ?4 c3 ?0 start/stop adrun controller up-counter start/stop control up/down control data bus start/stop control interrupt controller iad eiad v dd tr1 tr3 th rs cs r s th v ss adout v ss c ad
46 epson s1c60n02 technical manual chapter 4: peripheral circuits and operation (a/d converter) connect a reference resistance that only slightly changes resistance values according to environmental conditions between the oscillating i/o terminals rs and cs. connect a sensor that changes resistance values between the th and cs terminals. furthermore, by connecting a condenser between the cs and v ss , a cr oscillation circuit is com- pleted. this a/d converter performs cr oscillation using one of the two resistances connected to external devices. their oscilla- tion frequency serves as a clock from which the oscillation frequency is counted. difference in counted oscillation frequency can be evaluated in terms of the difference be- tween the respective resistance values. measurement results can be obtained from the changes in resistance values after correcting the difference according to the program. (1) external resistances and condenser connect a sensor (a variable resistance element such as a thermistor) between the th and cs terminals. next, set the reference value of the item to be measured (e.g. reference temperature in the case of temperature measurement) and connect the reference resistance equivalent to the sensor resistance value at the above reference value between the rs and cs terminals. an element that does not change due to temperature or other environmental conditions must be used as the reference resistance. connect an oscillating condenser that is used for cr oscillation of both the reference resistance and the sensor between the cs and v ss terminals. operation of a/d converter
s1c60n02 technical manual epson 47 chapter 4: peripheral circuits and operation (a/d converter) (2) oscillation circuit the cr oscillation circuit is designed so that either the reference resistance side or the sensor side can be oper- ated independently by the oscillation control circuit. a/d conversion begins when "1" is written in the adrun register (0f1h d0). at the same time, the oscillation circuit also turns on. at first, the circuit of the reference resistance side (rs) is operated by the oscillation control circuit. then, the circuit of the sensor side (th) turns on when counting by the oscillation clock of the reference resistance is terminated. each circuit performs the same oscillating operation as follows: the tr1 (tr2) turns on first, and the condenser connected between the cs and v ss terminals is charged through the reference resistance (sensor). if the voltage level of the cs terminal decreases, the tr1 (tr2) turns off and the tr3 turns on. as a result, the condenser becomes discharged, and oscillation is performed according to cr time con- stant. the time constant changes as the sensor resist- ance value fluctuates, producing a difference from the oscillation frequency of the reference resistance. oscillation waveforms are shaped by the schmitt trigger and transmitted to counter. the clock transmitted to the counter is also output from the adout terminal. as a result, oscillation frequency can be identified by the oscilloscope. since this monitor has no effect on oscilla- tion frequency, it can be used to adjust cr oscillation frequency. oscillation waveforms and waveforms output from the adout terminal are shown in figure 4.8.2. fig. 4.8.2 oscillation waveforms cs terminal adout v dd v ss v dd v ss
48 epson s1c60n02 technical manual chapter 4: peripheral circuits and operation (a/d converter) (3) counter the a/d converter incorporates two types of 16-bit counters. one is the up-counter c0?15 that counts the aforementioned oscillation clock, and the other is up/ down counter tc0?c15 that counts the internal clock for reference counting. each counter permits reading and writing on a 4-bit basis. the input unit of the up/down counter tc0?c15 incor- porates a multiplying circuit so that either the osc1 clock (typ. 32.768 khz) or its multiplication clock (typ. 65.536 khz) can be selected as an input clock. when a/d conversion is initiated by the adrun register, oscillation by the reference resistance begins first, and the up-counter c0?15 starts counting up according to the oscillation clock. at the same time, the up/down counter tc0?c15 starts counting up. timing in starting oscillation and starting counting up are shown in figure 4.8.3. the up-counter becomes enable at the falling edge of the first clock after cr oscillation is initiated and starts counting up from the falling edge of the next clock. the up/down counter becomes enable at the falling edge of the internal clock which is input immediately after the first cr oscillation clock has fallen. then, it starts counting up from the falling edge of the next inter- nal clock. fig. 4.8.3 counting up start timing adrun register cs terminal adout up-counter enable up-counter (c0) clock (up/down counter) up/down counter enable up/down counter (tc0) start start
s1c60n02 technical manual epson 49 chapter 4: peripheral circuits and operation (a/d converter) if the up-counter c0?15 becomes "0000h" due to over- flow, the sensor side of the oscillation circuit turns on, and the up-counter starts counting up according to the oscillation clock on the sensor side. the up/down counter tc0?c15 shifts to the counting- down mode at this point and starts counting down from the value measured as a result of oscillation by the reference resistance. timing in starting counting when oscillation is switched, is same as figure 4.8.3. when the up/down counter tc0?c15 has counted down to "0000h", the counting operation of both counters and cr oscillation stops, and an interrupt occurs. at the same time, the adrun register is set to "0", and the a/d converter circuit stops operation completely. the sensor is oscillated for the same period of time as the reference resistance is oscillated after the up/down counter tc0?c15 is set to "0000h" prior to a/d conver- sion. therefore, the difference in oscillation frequency can be measured from the values counted by the up-counter c0?15. since the reference resistance is oscillated until the up- counter c0?15 overflows, an appropriate initial value needs to be set before a/d conversion is started. if a smaller initial value is set, a longer counting period is possible, thereby ensuring more accurate detection. likewise, if the input clock of the up/down counter tc0 tc15 is set at 65 khz, the degree of precision is reduced. however, since cr oscillation frequency is normally set lower than the clock frequency of the up/down counter tc0?c15 to ensure accurate measurement, the up/ down counter tc0?c15 may overflow while counting the oscillation frequency of the reference resistance. if an overflow occurs, cr oscillation and a/d conversion is terminated immediately. also in such cases, the up/ down counter indicates "0000h", and interrupt occurs. however, it is impossible to judge whether the interrupt has occurred due to an overflow or normal termination.
50 epson s1c60n02 technical manual chapter 4: peripheral circuits and operation (a/d converter) note that correct measurement is impossible if an over- flow occurs. the initial value to be set depends on the measurable range by the sensor or where to set the reference resistance value within that range. the initial value must be set taking the above into con- sideration. convert the initial value into a complement (value sub- tracted from 0000h) before setting it on the up-counter c0?15. since the data output from the up-counter c0 c15 after a/d conversion matches data detected by the sensor, process the difference between that value and the initial value before it is converted into a complement according to the program and calculate the target value. the above operations are shown in figure 4.8.4. note - set the initial value of the up-counter c0 c15 taking into account the measurable range and the overflow of the up/down counter tc0 tc15. - if the up/down counter tc0 tc15 is measured after a/d conversion, it may not indicate "0000h". this is not due to incorrect timing in terminating a/d conversion but because the counting down clock is input after the control signal is output to the up-counter to terminate counting. fig. 4.8.4 sequence of a/d conversion up-counter (c0 c15) (0000h-n) (1) set the initial value (0000h-n) count up ffffh 0 0 count up : m up/down counter (tc0 tc15) 0000h 0000h count up : x x count down 0001h 0000h (2) start a/d conversion (set "1" on the adrun) (3) read the up-counter and process the m? value acoording to the program setting by software set the complement of the initial value n on the up-counter set "0000h" on the up /down counter oscillation by reference resistance switch cr oscillation when the up-counter overflows and shift the up/down counter to the counting-down mode when the value of the up/down counter reaches 0000h, oscillation and conting stops, and an interruption occurs. oscillation by sensor
s1c60n02 technical manual epson 51 chapter 4: peripheral circuits and operation (a/d converter) the a/d converter has a function which allows interrupt to occur after a/d conversion. when the up/down counter tc0?c15 is counted down to "0000h", both counters stop counting. the interrupt factor flag iad is set to "1" at the falling edge of the next clock. if the up/down counter tc0?c15 overflow during counting- up operation, the interrupt factor flag is set to "1" at the rising edge of the clock immediately after the counter reaches "0000h". this interrupt factor allows masking by the interrupt mask register eiad. if the eiad is set at "1", an interrupt occurs in the cpu. if the eiad is set at "0", the interrupt factor flag is set to "1". however, no interrupt will occur in the cpu. the interrupt factor flag is reset to "0" by a reading opera- tion. timing of interrupt by the a/d converter is shown in figure 4.8.5. interrupt function fig. 4.8.5 timing of a/d converter interrupt temperature measurement is possible with the a/d con- verter in which a thermistor is used as a sensor. elements to be connected and counter setting in the case of tempera- ture measurement are as follows: example: temperature measurement at -20 c to 70 c reference resistance ....... 49.8 k ? thermistor ...................... 50 k ? oscillating condenser ...... 2,200 pf usage example of the a/d converter adrun register adout up-counter data up/down counter clock up/down counter data interrupt n n+1 n+2 0 123 fffe ffff 0 x x-1 x-2 x-1 x-2 x-3 x-3 3210 m m-1 oscillation with reference resistor oscillation with sensor 12
52 epson s1c60n02 technical manual chapter 4: peripheral circuits and operation (a/d converter) when the above elements are connected, the oscillation frequency of the reference resistance becomes about 10 khz, and the oscillation frequency of the thermistor varies within the range of about 1 khz to 50 khz at -20? to 70?. reference resistance is adjusted to the thermistor resistance value at 25?. in addition, figure 4.8.6 indicates the resistance and oscil- lation frequency ratio typ at the time of a/d conversion. fig. 4.8.6 resistance and oscillation frequency ratio 10 k 0.1 ( ) 50 k 100 k 500 k 1.0 5.0 resistance value oscillation frequency ratio ? ? resistance and oscillation frequency ratio of a/d conversion circuit for 50 k , set the oscillation frequency to 1.
s1c60n02 technical manual epson 53 chapter 4: peripheral circuits and operation (a/d converter) table 4.8.2 shows the a/d converter control bits and their addresses. control of a/d converter table 4.8.2 control bits of clock timer * 1 initial value following initial reset * 4 reset (0) immediately after being read * 2 not set in the circuit * 5 always "0" when being read * 3 undefined * 6 refer to main manual address comment register d3 d2 d1 d0 name init 1 0 *1 0e4h tc0 r/w tc3 tc2 tc1 tc0 up/down counter data tc3 up/down counter data tc2 up/down counter data tc1 up/down counter data tc0 (lsb) 1 1 1 1 0 0 0 0 tc1 tc2 tc3 *3 *3 *3 *3 tc4 r/w tc7 tc6 tc5 tc4 up/down counter data tc7 up/down counter data tc6 up/down counter data tc5 up/down counter data tc4 1 1 1 1 0 0 0 0 tc5 tc6 tc7 0e5h *3 *3 *3 *3 0e6h tc8 r/w tc11 tc10 tc9 tc8 up/down counter data tc11 up/down counter data tc10 up/down counter data tc9 up/down counter data tc8 1 1 1 1 0 0 0 0 tc9 tc10 tc11 *3 *3 *3 *3 0e7h tc12 r/w tc15 tc14 tc13 tc12 up/down counter data tc15 (msb) up/down counter data tc14 up/down counter data tc13 up/down counter data tc12 1 1 1 1 0 0 0 0 tc13 tc14 tc15 *3 *3 *3 *3 0f5h c0 r/w c3 c2 c1 c0 up-counter data c3 up-counter data c2 up-counter data c1 up-counter data c0 (lsb) 1 1 1 1 0 0 0 0 c1 c2 c3 *3 *3 *3 *3 c4 r/w c7 c6 c5 c4 up-counter data c7 up-counter data c6 up-counter data c5 up-counter data c4 1 1 1 1 0 0 0 0 c5 c6 c7 0f6h *3 *3 *3 *3 0f7h c8 r/w c11 c10 c9 c8 up-counter data c11 up-counter data c10 up-counter data c9 up-counter data c8 1 1 1 1 0 0 0 0 c9 c10 c11 *3 *3 *3 *3 0f8h c12 r/w c15 c14 c13 c12 up-counter data c15 (msb) up-counter data c14 up-counter data c13 up-counter data c12 1 1 1 1 0 0 0 0 c13 c14 c15 *3 *3 *3 *3 0ech eiad r/w 0 0 0 eiad 0 interrupt mask register (a/d) enable mask 0 0 r 0 *5 *5 *5 0f0h iad 0 0 0 iad 0 interrupt factor flag (a/d) yes no 0 0 0 *5 *5 *5 *4 r 0f1h adrun r/w 0 0 0 adrun 0 a/d conversion start/stop start stop 0 0 r 0 *5 *5 *5 0feh adclk r/w 0 0 0 adclk 0 a/d clock selection 65 khz/32 khz 65 khz 32 khz 0 0 r 0 *5 *5 *5
54 epson s1c60n02 technical manual chapter 4: peripheral circuits and operation (a/d converter) up/down counter (0e4h 0e7h) writing and reading is possible on a 4-bit basis by the up/ down counter that is used to adjust the cr oscillation time between the reference resistance and the variable resistance elements. the up/down counter counts up during oscillation of the reference resistance and counts down from the value it reached when counting up to "0000h" during oscillation of the sensor. "0000h" needs to be entered in the counter prior to a/d conversion in order to adjust the counting time of both counts. after an initial reset, data in this counter become indefinite. up-counter (0f5h 0f8h) this counter counts up according to the cr oscillation clock. it permits writing and reading on a 4-bit basis. the complement of the number of clocks to be counted by the oscillation of the reference resistance, must be entered in this counter prior to a/d conversion. if a/d conversion is initiated, the counter counts up from the set initial value, first according to the oscillation clock of the reference resistance. when the counter reaches "0000h" due to overflow, the oscillation of the reference resistance stops, and the sensor starts oscillating. the counter contin- ues counting according to the sensor oscillation clock. counting time during the oscillation of the reference resist- ance is calculated by the up/down counter tc0?c15. up- counter c0?15 stops counting when the same period of time elapses. difference from the reference resistance can be evaluated from the value indicated by the counter when it stops. calculate the target value by processing the above difference according to the program. measurable range and the overflow of the up/down counter tc0?c15 must be taken into account when setting an initial value to be entered prior to a/d conversion. after an initial reset, data in this counter become indefinite. tc0 tc15 c0 c15
s1c60n02 technical manual epson 55 chapter 4: peripheral circuits and operation (a/d converter) input clock selection (0feh d0) select the input clock of the up/down counter tc0?c15. when "1" is written: 65 khz when "0" is written: 32 khz reading: valid select the output clock of the multiplying circuit for the counting operation of the up/down counter tc0?c15. when "1" is written in the adclk, 65 khz, a multitude of the osc1 clock is selected. when "0" is written, the osc1 clock is selected at 32 khz. if 65 khz is selected, a/d conversion becomes more accu- rate. however, the initial value must be set on the up- counter c0?15 so that the up/down counter tc0?c15 will not overflow while cr oscillation is being counted. after an initial reset, adclk is set to "0". a/d conversion start/stop (0f1h d0) start a/d conversion. when "1" is written: a/d conversion starts when "0" is written: a/d conversion stops reading: valid when "1" is written in the adrun, a/d conversion begins. the register remains at "1" during a/d conversion and is set to "0" when a/d conversion is terminated. when "0" is written in the adrun during a/d conversion, a/d conversion is paused. adrun is set to "0" at initial reset, when the up/down counter overflows or when measurement is finished. interrupt mask register (0ech d0) select whether to mask interrupt with the a/d converter. when "1" is written: enable when "0" is written: mask reading: valid the a/d converter interrupt is permitted when "1" is written in the eiad. when "0" is written, interrupt is masked. after an initial reset, this register is set to "0". adrun eiad adclk
56 epson s1c60n02 technical manual chapter 4: peripheral circuits and operation (a/d converter) iad interrupt factor flag (0f0h d0) this flag indicates interrupt caused by the a/d converter. when "1" is read: interrupt has occurred when "0" is read: interrupt has not occurred writing: invalid iad is set to "1" when a/d conversion is terminated (when the up/down counter counted up or down to "0000h"). from the status of this flag, the software can decide whether an a/d converter interrupt has occurred. this flag is reset when the software has read it. reading of interrupt factor flag is available at ei, but be careful in the following cases. if the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not be generated. after an initial reset, this flag is set to "0".
s1c60n02 technical manual epson 57 chapter 4: peripheral circuits and operation (heavy load protection function) 4.9 heavy load protection function the s1c60n02 series has a heavy load protection function for when the battery load becomes heavy and the supply voltage drops, such as when an external buzzer sounds or an external lamp lights. this function works in the heavy load protection mode. the normal mode changes to the heavy load protection mode in the following case: when the software changes the mode to the heavy load protection mode (hlmod = "1") in the heavy load protection mode, the internally regulated voltage is switched to the high-stability mode from the low current consumption mode. consequently, more current is consumed in the heavy load protection mode than in the normal mode. unless necessary, do not select the heavy load protection mode with the software. operation of heavy load protection function
58 epson s1c60n02 technical manual chapter 4: peripheral circuits and operation (heavy load protection function) table 4.9.1 shows the control bits and their addresses for the heavy load protection function. table 4.9.1 control bits for heavy load protection function control of heavy load protection function heavy load protection mode on/off (0fah d3) when "1" is written: heavy load protection mode on when "0" is written: heavy load protection mode off reading: valid when hlmod is set to "1", the ic enters the heavy load protection mode. in the heavy load protection mode, the consumed current becomes larger. unless necessary, do not select the heavy load protection mode with the software. hlmod address comment register d3 d2 d1 d0 name init 1 0 *1 0fah 0 hlmod 0 0 0 0 heavy load protection mode register heavy normal 0 0 hlmod r/w *5 *5 *5 r * 1 initial value following initial reset * 2 not set in the circuit * 3 undefined * 4 reset (0) immediately after being read * 5 always "0" when being read * 6 refer to main manual
s1c60n02 technical manual epson 59 chapter 4: peripheral circuits and operation (interrupt and halt) interrupt and halt the s1c60n02 series provides the following interrupt set- tings, each of which is maskable. external interrupt: input interrupt (one) internal interrupt: timer interrupt (one) a/d converter interrupt (one) to enable interrupts, the interrupt flag must be set to "1" (ei) and the necessary related interrupt mask registers must be set to "1" (enable). when an interrupt occurs, the inter- rupt flag is automatically reset to "0" (di) and interrupts after that are inhibited. when a halt instruction is input, the cpu operating clock stops and the cpu enters the halt state. the cpu is reacti- vated from the halt state when an interrupt request occurs. figure 4.10.1 shows the configuration of the interrupt circuit. 4.10 fig. 4.10.1 configuration of interrupt circuit k00 eik00 k01 eik01 k02 eik02 k03 eik03 iad eiad it2 eit2 it8 eit8 it32 eit32 ik0 (msb) : : (lsb) program counter of cpu (three low-order bits) interrupt vector interrupt factor flag interrupt mask register interrupt flag int (interrupt request)
60 epson s1c60n02 technical manual chapter 4: peripheral circuits and operation (interrupt and halt) table 4.10.1 shows the factors that generate interrupt requests. the interrupt factor flags are set to "1" depending on the corresponding interrupt factors. the cpu is interrupted when the following two conditions occur and an interrupt factor flag is set to "1". ?the corresponding mask register is "1" (enabled) ?the interrupt flag is "1" (ei) the interrupt factor flag is a read-only register, but can be reset to "0" when the register data is read. after an initial reset, the interrupt factor flags are reset to "0". interrupt factors reading of interrupt factor flags is available at ei, but be careful in the following cases. if the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. be very careful when interrupt factor flags are in the same address. note table 4.10.1 interrupt factors interrupt factor colck timer 2 hz falling edge colck timer 8 hz falling edge colck timer 32 hz falling edge a/d converter a/d conversion completion input data (k00?03) rising edge interrupt factor flag it2 it8 it32 iad ik0 (0f0h d0) (0edh d0) (0efh d2) (0efh d1) (0efh d0)
s1c60n02 technical manual epson 61 chapter 4: peripheral circuits and operation (interrupt and halt) the interrupt factor flags can be masked by the correspond- ing interrupt mask registers. the interrupt mask registers are read/write registers. they are enabled (interrupt en- abled) when "1" is written to them, and masked (interrupt disabled) when "0" is written to them. after an initial reset, the interrupt mask register is set to "0". table 4.10.2 shows the correspondence between interrupt mask registers and interrupt factor flags. specific masks and factor flags for inter- rupt table 4.10.2 interrupt mask registers and interrupt factor flags interrupt mask register interrupt factor flag (0ebh d2) (0ebh d1) (0ebh d0) (0ech d0) (0e8h d3) (0e8h d2) (0e8h d1) (0e8h d0) it2 it8 it32 iad (0efh d2) (0efh d1) (0efh d0) (0f0h d0) ik0 (0edh d0) eit2 eit8 eit32 eiad eik03* eik02* eik01* eik00* * there is an interrupt mask register for each input port pin. when an interrupt request is input to the cpu, the cpu begins interrupt processing. after the program being exe- cuted is suspended, interrupt processing is executed in the following order: ? the address data (value of the program counter) of the program step to be executed next is saved on the stack (ram). ? the interrupt request causes the value of the interrupt vector (page 1, 01h?7h) to be loaded into the program counter. ? the program at the specified address is executed (execu- tion of interrupt processing routine). the processing in steps 1 and 2, above, takes 12 cycles of the cpu system clock. interrupt vectors note
62 epson s1c60n02 technical manual chapter 4: peripheral circuits and operation (interrupt and halt) control of interrupt table 4.10.3 shows the interrupt control bits and their addresses. table 4.10.3 interrupt control bits eit32, eit8, eit2 it32, it8, it2 eiad iad eik00?ik03 ik0 * 1 initial value following initial reset * 2 not set in the circuit * 3 undefined * 4 reset (0) immediately after being read * 5 always "0" when being read * 6 refer to main manual interrupt mask registers (0ebh d0?2) interrupt factor flags (0efh d0?2) see 4.7, "clock timer". interrupt mask register (0ech d0) interrupt factor flag (0f0h d0) see 4.8, "a/d converter". interrupt mask registers (0e8h) interrupt factor flag (0edh d0) see 4.3, "input ports". address comment register d3 d2 d1 d0 name init 1 0 *1 0e8h eik00 r/w eik03 eik02 eik01 eik00 0 0 0 0 interrupt mask register k03 interrupt mask register k02 interrupt mask register k01 interrupt mask register k00 enable enable enable enable mask mask mask mask eik01 eik02 eik03 0ebh eit32 0 eit2 eit8 eit32 0 0 0 interrupt mask register (clock timer) 2 hz interrupt mask register (clock timer) 8 hz interrupt mask register (clock timer) 32 hz enable enable enable mask mask mask eit8 r/w eit2 0 r *5 0ech eiad r/w 0 0 0 eiad 0 interrupt mask register (a/d) enable mask 0 0 r 0 *5 *5 *5 0edh ik0 0 0 0 ik0 0 interrupt factor flag (k00 k03) yes no 0 0 0 *5 *5 *5 *4 r 0efh it32 r 0 it2 it8 it32 0 0 0 interrupt factor flag (clock timer) 2 hz interrupt factor flag (clock timer) 8 hz interrupt factor flag (clock timer) 32 hz yes yes yes no no no it8 it2 0 *5 *4 *4 *4 0f0h iad 0 0 0 iad 0 interrupt factor flag (a/d) yes no 0 0 0 *5 *5 *5 *4 r
s1c60n02 technical manual epson 63 chapter 5: basic external wiring diagram basic external wiring diagram (1) piezo buzzer single terminal driving chapter 5 ca cb v l1 v l2 v l3 v dd osc1 osc2 v s1 reset test vss c 1 c g c 2 x'tal 1.5 v or 3.0 v piezo buzzer r01 k00 k03 p00 p03 r00 r02 r03 i i/o o seg0 seg19 com0 com3 lcd panel s1c60n02/60l02 coil cp rs th cs r s th capacitors (c 3 ? 5 ) are connected. connection depending on power supply and lcd panel specification. please refer to page 7. c ad x'tal c g c 1 ? 5 cp th r s c ad crystal oscillator trimmer capacitor capacitor capacitor thermistor resistor capacitor 32,768 hz ci(max) = 35 k ? 5?5 pf 0.1 f 3.3 f 50 k ? 49.8 k ? 2,200 pf
64 epson s1c60n02 technical manual chapter 5: basic external wiring diagram piezo buzzer r00 k00 k03 p00 p03 r02 r03 i i/o o seg0 seg19 com0 com3 lcd panel s1c60n02/60l02 rs th cs r01 ca cb v l1 v l2 v l3 v dd osc1 osc2 v s1 reset test vss c 1 c g c 2 x'tal 1.5 v or 3.0 v cp c ad r s th capacitors (c 3 ? 5 ) are connected. connection depending on power supply and lcd panel specification. please refer to page 7. (2) piezo buzzer direct driving x'tal c g c 1 ? 5 cp th r s c ad crystal oscillator trimmer capacitor capacitor capacitor thermistor resistor capacitor 32,768 hz ci(max) = 35 k ? 5?5 pf 0.1 f 3.3 f 50 k ? 49.8 k ? 2,200 pf
s1c60n02 technical manual epson 65 chapter 6: electrical characteristics chapter 6 electrical characteristics 6.1 absolute maximum rating s1c60l02 s1c60n02 power voltage input voltage (1) input voltage (2) operating temperature storage temperature soldering temperature / time allowable dissipation item symbol v ss v i v iosc topr tstg tsol p d rated value -5.0 to 0.5 vss-0.3 to 0.5 vss-0.3 to 0.5 -20 to 70 -65 to 150 260 c, 10sec (lead section) 250 unit v v v c c mw (v dd =0v) *1 power voltage input voltage (1) input voltage (2) operating temperature storage temperature soldering temperature / time allowable dissipation item symbol v ss v i v iosc topr tstg tsol p d rated value -5.0 to 0.5 vss-0.3 to 0.5 vss-0.3 to 0.5 -20 to 70 -65 to 150 260 c, 10sec (lead section) 250 unit v v v c c mw (v dd =0v) *1 * 1 in case of qfp6-60 pin plastic package * 1 in case of qfp6-60 pin plastic package
66 epson s1c60n02 technical manual chapter 6: electrical characteristics 6.2 recommended operating conditions s1c60n02 s1c60l02 * 1 when switching to the heavy load protection mode. (for details, refer to section 4.9). * 2 the voltage which can be displayed on the lcd panel will differ according to the characteristics of the lcd panel. * 3 when there is no software correspondence during cr oscillation or crystal oscilla- tion. item power voltage oscillation frequency booster capacitor capacitor between v dd and v s1 symbol v ss f osc1 f osc2 c 1 c 2 condition v dd =0v crystal oscillation cr oscillation, r=420k ? min -3.5 0.1 0.1 typ -3.0 32,768 65 unit v hz khz f f max -1.8 80 (ta=-20 to 70 c) item power voltage oscillation frequency booster capacitor capacitor between v dd and v s1 symbol v ss f osc1 f osc2 c 1 c 2 condition v dd =0v v dd =0v, with software correspondence crystal oscillation cr oscillation, r=420k ? min -2.0 -2.0 0.1 0.1 typ -1.5 -1.5 32,768 65 unit v v hz khz f f max -1.2 -0.9 80 *2 *1 *3 (ta=-20 to 70 c)
s1c60n02 technical manual epson 67 chapter 6: electrical characteristics 6.3 dc characteristics s1c60n02 unless otherwise specified v dd =0 v, v ss =-3.0 v, fosc=32,768 hz, ta=25?c, v s1 , v l1 , v l2 and v l3 are internal voltages, and c 1 =c 2 =0.1 f item symbol v ih1 v ih2 v il1 v il2 i ih1 i ih2 i ih3 i il i oh1 i oh2 i oh3 i ol1 i ol2 i ol3 i oh4 i ol4 i oh5 i ol5 i oh6 i ol6 condition min 0.2 v ss 0.15 v ss v ss v ss 0 5 30 -0.5 3.0 3.0 3.0 3 3 300 typ unit v v v v a a a a ma ma ma ma ma ma a a a a a a max 0 0 0.8 v ss 0.85 v ss 0.5 16 100 0 -1.0 -1.0 -1.0 -3 -3 -300 k00 k03, p00 p03 reset, test k00 k03, p00 p03 reset, test k00 k03, p00 p03 k00 k03 p00 p03 reset, test k00 k03, p00 p03 reset, test r02, r03, p00 p03 r00, r01 adout r02, r03, p00 p03 r00, r01 adout com0 com3 seg0 seg19 seg0 seg19 high level input voltage (1) high level input voltage (2) low level input voltage (1) low level input voltage (2) high level input current (1) high level input current (2) high level input current (3) low level input current high level output current (1) high level output current (2) high level output current (3) low level output current (1) low level output current (2) low level output current (3) common output current segment output current (during lcd output) segment output current (during dc output) v ih1 =0v without pull down resistor v ih2 =0v with pull down resistor v ih3 =0v with pull down resistor v il =v ss v oh1 =0.1 v ss v oh2 =0.1 v ss (built-in protection resistance) v oh3 =-1.0v v ol1 =0.9 v ss v ol2 =0.9 v ss (built-in protection resistance) v ol3 =-2.0v v oh4 =-0.05v v ol4 =v l3 +0.05v v oh5 =-0.05v v ol5 =v l3 +0.05v v oh6 =0.1 v ss v ol6 =0.9 v ss
68 epson s1c60n02 technical manual chapter 6: electrical characteristics s1c60l02 unless otherwise specified v dd =0 v, v ss =-1.5 v, fosc=32,768 hz, ta=25?c, v s1 , v l1 , v l2 and v l3 are internal voltages, and c 1 =c 2 =0.1 f item symbol v ih1 v ih2 v il1 v il2 i ih1 i ih2 i ih3 i il i oh1 i oh2 i oh3 i ol1 i ol2 i ol3 i oh4 i ol4 i oh5 i ol5 i oh6 i ol6 condition min 0.2 v ss 0.15 v ss v ss v ss 0 2.0 9.0 -0.5 700 700 700 3 3 130 typ unit v v v v a a a a a a a a a a a a a a a a max 0 0 0.8 v ss 0.85 v ss 0.5 16 100 0 -200 -200 -200 -3 -3 -100 k00 k03, p00 p03 reset, test k00 k03, p00 p03 reset, test k00 k03, p00 p03 k00 k03 p00 p03 reset, test k00 k03, p00 p03 reset, test r02, r03, p00 p03 r00, r01 adout r02, r03, p00 p03 r00, r01 adout com0 com3 seg0 seg19 seg0 seg19 high level input voltage (1) high level input voltage (2) low level input voltage (1) low level input voltage (2) high level input current (1) high level input current (2) high level input current (3) low level input current high level output current (1) high level output current (2) high level output current (3) low level output current (1) low level output current (2) low level output current (3) common output current segment output current (during lcd output) segment output current (during dc output) v ih1 =0v without pull down resistor v ih2 =0v with pull down resistor v ih3 =0v with pull down resistor v il =v ss v oh1 =0.1 v ss v oh2 =0.1 v ss (built-in protection resistance) v oh3 =-0.5v v ol1 =0.9 v ss v ol2 =0.9 v ss (built-in protection resistance) v ol3 =-1.0v v oh4 =-0.05v v ol4 =v l3 +0.05v v oh5 =-0.05v v ol5 =v l3 +0.05v v oh6 =0.1 v ss v ol6 =0.9 v ss
s1c60n02 technical manual epson 69 chapter 6: electrical characteristics analog circuit characteristics and power current con- sumption s1c60n02 (normal operating mode) unless otherwise specified v dd =0 v, v ss =-3.0 v, fosc=32,768 hz, ta=25?c, c g =25 pf, v s1 , v l1 , v l2 and v l3 are internal voltages, and c 1 =c 2 =0.1 f (during a/d conversion: r s =49.8 k ? ? s1c60n02 (heavy load protection mode) unless otherwise specified v dd =0 v, v ss =-3.0 v, fosc=32,768 hz, ta=25?c, c g =25 pf, v s1 , v l1 , v l2 and v l3 are internal voltages, and c 1 =c 2 =0.1 f (during a/d conversion: r s =49.8 k ? ? 6.4 symbol v l1 v l2 v l3 i op condition connect 1m ? load resistor between v dd and v l1 (without panel load) connect 1m ? load resistor between v dd and v l2 (without panel load) connect 1m ? load resistor between v dd and v l3 (without panel load) min 1/2 v l2 -0.1 3/2 v l2 -0.1 typ v ss 1.0 2.5 30 unit v v v a a a max 1/2 v l2 0.9 3/2 v l2 0.9 2.5 5.0 40 during halt during execution without panel load during a/d conversion (halt) item internal voltage power current consumption item internal voltage power current consumption symbol v l1 v l2 v l3 i op condition connect 1m ? load resistor between v dd and v l1 (without panel load) connect 1m ? load resistor between v dd and v l2 (without panel load) connect 1m ? load resistor between v dd and v l3 (without panel load) min 1/2 v l2 -0.1 3/2 v l2 -0.1 typ v ss 2.0 5.5 31 unit v v v a a a max 1/2 v l2 0.85 3/2 v l2 0.85 5.5 10.0 41.5 during halt during execution without panel load during a/d conversion (halt)
70 epson s1c60n02 technical manual chapter 6: electrical characteristics s1c60l02 (normal operating mode) unless otherwise specified v dd =0 v, v ss =-1.5 v, fosc=32,768 hz, ta=25?c, c g =25 pf, v s1 , v l1 , v l2 and v l3 are internal voltages, and c 1 =c 2 =0.1 f (during a/d conversion: r s =49.8 k ? ? s1c60l02 (heavy load protection mode) unless otherwise specified v dd =0 v, v ss =-1.5 v, fosc=32,768 hz, ta=25?c, c g =25 pf, v s1 , v l1 , v l2 and v l3 are internal voltages, and c 1 =c 2 =0.1 f (during a/d conversion: r s =49.8 k ? ? internal voltage power current consumption symbol v l1 v l2 v l3 i op condition connect 1m ? load resistor between v dd and v l1 (without panel load) connect 1m ? load resistor between v dd and v l2 (without panel load) connect 1m ? load resistor between v dd and v l3 (without panel load) min 2 v l1 -0.1 3 v l1 -0.1 typ v ss 1.0 2.5 30 unit v v v a a a max 2 v l1 0.9 3 v l1 0.9 2.5 5.0 40 during halt during execution without panel load during a/d conversion (halt) item internal voltage power current consumption symbol v l1 v l2 v l3 i op condition connect 1m ? load resistor between v dd and v l1 (without panel load) connect 1m ? load resistor between v dd and v l2 (without panel load) connect 1m ? load resistor between v dd and v l3 (without panel load) min 2 v l1 -0.1 3 v l1 -0.1 typ v ss 2.0 5.5 31 unit v v v a a a max 2 v l1 0.85 3 v l1 0.85 5.5 10.0 41.5 during halt during execution without panel load during a/d conversion (halt) item
s1c60n02 technical manual epson 71 chapter 6: electrical characteristics s1c60n02 (cr, normal operating mode) unless otherwise specified v dd =0 v, v ss =-3.0 v, fosc=65 khz, ta=25?c, c g =25 pf, v s1 , v l1 , v l2 and v l3 are internal voltages, and c 1 =c 2 =0.1 f, recommended external resistance for cr oscillation = 420 k ? ? ? s1c60n02 (cr, heavy load protection mode) unless otherwise specified v dd =0 v, v ss =-3.0 v, fosc=65 khz, ta=25?c, c g =25 pf, v s1 , v l1 , v l2 and v l3 are internal voltages, and c 1 =c 2 =0.1 f, recommended external resistance for cr oscillation = 420 k ? ? ? internal voltage power current consumption symbol v l1 v l2 v l3 i op condition connect 1m ? load resistor between v dd and v l1 (without panel load) connect 1m ? load resistor between v dd and v l2 (without panel load) connect 1m ? load resistor between v dd and v l3 (without panel load) min 1/2 v l2 -0.1 3/2 v l2 -0.1 typ v ss 8.0 15.0 37 unit v v v a a a max 1/2 v l2 0.9 3/2 v l2 0.9 15.0 20.0 52.5 during halt during execution without panel load during a/d conversion (halt) item internal voltage power current consumption symbol v l1 v l2 v l3 i op condition connect 1m ? load resistor between v dd and v l1 (without panel load) connect 1m ? load resistor between v dd and v l2 (without panel load) connect 1m ? load resistor between v dd and v l3 (without panel load) min 1/2 v l2 -0.1 3/2 v l2 -0.1 typ v ss 16.0 30.0 45 unit v v v a a a max 1/2 v l2 0.85 3/2 v l2 0.85 30.0 40.0 57.5 during halt during execution without panel load during a/d conversion (halt) item
72 epson s1c60n02 technical manual chapter 6: electrical characteristics s1c60l02 (cr, normal operating mode) unless otherwise specified v dd =0 v, v ss =-1.5 v, fosc=65 khz, ta=25?c, c g =25 pf, v s1 , v l1 , v l2 and v l3 are internal voltages, and c 1 =c 2 =0.1 f, recommended external resistance for cr oscillation = 420 k ? ? ? s1c60l02 (cr, heavy load protection mode) unless otherwise specified v dd =0 v, v ss =-1.5 v, fosc=65 khz, ta=25?c, c g =25 pf, v s1 , v l1 , v l2 and v l3 are internal voltages, and c 1 =c 2 =0.1 f, recommended external resistance for cr oscillation = 420 k ? ? ? internal voltage power current consumption symbol v l1 v l2 v l3 i op condition connect 1m ? load resistor between v dd and v l1 (without panel load) connect 1m ? load resistor between v dd and v l2 (without panel load) connect 1m ? load resistor between v dd and v l3 (without panel load) min 2 v l1 -0.1 3 v l1 -0.1 typ v ss 8.0 15.0 37 unit v v v a a a max 2 v l1 0.9 3 v l1 0.9 15.0 20.0 52.5 during halt during execution without panel load during a/d conversion (halt) item internal voltage power current consumption symbol v l1 v l2 v l3 i op condition connect 1m ? load resistor between v dd and v l1 (without panel load) connect 1m ? load resistor between v dd and v l2 (without panel load) connect 1m ? load resistor between v dd and v l3 (without panel load) min 2 v l1 -0.1 3 v l1 -0.1 typ v ss 16.0 30.0 45 unit v v v a a a max 2 v l1 0.85 3 v l1 0.85 30.0 40.0 57.5 during halt during execution without panel load during a/d conversion (halt) item
s1c60n02 technical manual epson 73 chapter 6: electrical characteristics oscillation characteristics oscillation characteristics will vary according to different conditions. use the following characteristics are as reference values. s1c60n02 unless otherwise specified v dd =0 v, v ss =-3.0 v, crystal: q13mc146, c g =25 pf, c d =built-in, ta=25?c 6.5 s1c60l02 unless otherwise specified v dd =0 v, v ss =-1.5 v, crystal: q13mc146, c g =25 pf, c d =built-in, ta=25?c * 1 items enclosed in parentheses ( ) are those used when operating at heavy load protection mode. item oscillation start voltage oscillation stop voltage built-in capacity (drain) frequency voltage deviation frequency ic deviation frequency adjustment range higher harmonic oscillation start voltage allowable leak resistance symbol vsta (vss) vstp (vss) c d f/v f/ic f/c g v hho (vss) r leak condition min -1.8 -1.8 -10 40 200 typ 20 unit v v pf ppm ppm ppm v m ? max 5 10 -3.6 t sta 5sec t stp 10sec including the parasitic capacity inside the ic vss=-1.8 to -3.5v c g =5 25pf c g =5pf between osc1 and v dd , and between v ss and osc1 item oscillation start voltage oscillation stop voltage built-in capacity (drain) frequency voltage deviation frequency ic deviation frequency adjustment range higher harmonic oscillation start voltage allowable leak resistance symbol vsta (vss) vstp (vss) c d f/v f/ic f/c g v hho (vss) r leak condition min -1.2 -1.2 -10 40 200 typ 20 unit v v pf ppm ppm ppm v m ? max 5 10 -2.0 t sta 5sec t stp 10sec including the parasitic capacity inside the ic vss=-1.2 to -2.0v (-0.9) c g =5 25pf c g =5pf between osc1 and v dd , and between v ss and osc1 *1
74 epson s1c60n02 technical manual chapter 6: electrical characteristics s1c60n02 (cr) unless otherwise specified v dd =0 v, v ss =-3.0 v, r cr =420 k ? s1c60l02 (cr) unless otherwise specified v dd =0 v, v ss =-1.5 v, r cr =420 k ? item oscillation frequency dispersion oscillation start voltage oscillation start time oscillation stop voltage symbol fosc vsta t sta vstp condition vss=-1.8 to -3.5v min -20 -1.8 -1.8 typ 65khz 3 unit % v ms v max 20 item oscillation frequency dispersion oscillation start voltage oscillation start time oscillation stop voltage symbol fosc vsta t sta vstp condition vss=-1.2 to -2.0v min -20 -1.2 -1.2 typ 65khz 3 unit % v ms v max 20
s1c60n02 technical manual epson 75 chapter 7: package chapter 7 package 7.1 plastic package 14 0.2 17.6 0.4 31 45 14 0.2 17.6 0.4 16 30 index 0.35 0.1 15 1 60 46 2.7 0.1 0.1 3.1 max 1.8 0.85 0.2 0 10 0.15 0.05 0.8 qfp6-60pin (unit: mm)
76 epson s1c60n02 technical manual chapter 7: package ceramic package for test samples 7.2 dip-64pin (unit: mm) 22.8 23.1 78.7 2.54 pin no. 1 2 31 32 34 33 64 63 index mark 81.3 no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 pin name n.c. seg17 seg18 seg19 com0 com1 com2 com3 n.c. v l3 v l2 v l1 ca cb v ss v dd no. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 pin name osc1 osc2 v s1 p00 p01 p02 p03 n.c. n.c. n.c. k00 k01 k02 k03 r00 r01 no. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 pin name r02 r03 rs th cs adout n.c. n.c. n.c. n.c. seg0 seg1 seg2 seg3 seg4 seg5 no. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 pin name seg6 seg7 seg8 seg9 seg10 seg11 n.c. n.c. test reset seg12 seg13 seg14 seg15 seg16 n.c. n.c. = no connection
s1c60n02 technical manual epson 77 chapter 8: pad layout chapter 8 pad layout 8.1 diagram of pad layout y x (0, 0) 2.56 mm 2.75 mm 12 11 10 9 8 7 6 5 4 3 2 1 26 25 24 23 22 21 20 19 18 17 16 15 14 13 40 39 38 37 36 35 34 33 32 31 30 29 28 27 52 51 50 49 48 47 46 45 44 43 42 41
78 epson s1c60n02 technical manual chapter 8: pad layout 8.2 pad coordinates (unit: m) pad no 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 pad no 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 pad name seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 test reset seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 com0 com1 com2 com3 pad name v l3 v l2 v l1 ca cb v ss v dd osc1 osc2 v s1 p00 p01 p02 p03 k00 k01 k02 k03 r00 r01 r02 r03 rs th cs adout x 608 478 348 218 88 -42 -172 -302 -432 -562 -692 -822 -1,209 -1,209 -1,209 -1,209 -1,209 -1,209 -1,209 -1,209 -1,209 -1,209 -1,209 -1,209 -1,209 -1,209 x -1,162 -1,032 -902 -771 -641 16 147 281 434 587 766 896 1,026 1,156 1,209 1,209 1,209 1,209 1,209 1,209 1,209 1,209 1,209 1,209 1,209 1,209 y 1,111 1,111 1,111 1,111 1,111 1,111 1,111 1,111 1,111 1,111 1,111 1,111 978 845 714 584 454 324 194 64 -66 -196 -361 -499 -629 -760 y -1,111 -1,111 -1,111 -1,111 -1,111 -1,111 -1,111 -1,111 -1,111 -1,111 -1,111 -1,111 -1,111 -1,111 -674 -544 -413 -283 -59 71 301 431 573 711 893 1,069
s1c60n02 technical manual epson 79 appendix: technical information technical information this chapter presents the information necessary for designing a thermometer using a seiko epson s1c60n02 and a thermistor manufactured by ishizuka denshi inc. appendices appendix a design steps for designing thermometer this section describes the design steps for the thermometer using the s1c60n02 and the thermistor. thermometer design steps the following shows the design steps: (1) obtain the external capacitor value and the oscillation fre- quency. (2) obtain the initial value that is set to the up-counter of the a/d converter. (3) after a/d conversion, calculate the displayed temperature from the counter value that has been set in the up-counter. details of these steps are described in later sections. before designing the thermometer, the measured temperature range, standard temperature, and thermistor to be used have to be determined. measured temperature range determine for your application. standard temperature the standard temperature is the most precise value. determine the standard temperature as the temperature that you want to be the most precise. thermistor select the thermistor considering the measured temperature range and the standard temperature. it also should match the ic. note that this document assumes the following: measured temperature range: -30??0? standard temperature: 20? thermistor: thermistor 103at (compatibility with s1c60n02)
80 epson s1c60n02 technical manual appendix: technical information the following a/d converter circuit diagram is shown for your reference. fig. a.1 a/d converter configuration tr2 multiplying circuit interrupt request osc1 clock 32 khz or 65 khz tc15 ?c12 tc11 ?c8 tc7 ?c4 tc3 ?c0 up/down counter adclk c15 ?12 c11 ?8 c7 ?4 c3 ?0 start/stop adrun controller up-counter start/stop control up/down control data bus start/stop control interrupt controller iad eiad v dd tr1 tr3 th rs cs r 1 r 2 v ss adout v ss c external capacitor standard resistor thermistor
s1c60n02 technical manual epson 81 appendix: technical information how to obtain capacitor value and oscillation frequency the standard resistor and the thermistor are oscillated according to s1c60n02 a/d converter principles. it is necessary to determine the value of the external capacitor for the oscillation. this section describes how to determine the standard resistor value, the external capacitor value and the cr oscillation fre- quency. table a.1 item standard resistor value (r 1 ) computation of capacitor for oscillation computation of frequency from the standard resistance description thermistor resistance value at the standard temperature. the relationship between the frequency, capacitor, and the resistor is as follows: f = k f: oscillation frequency cr k: cr oscillation frequency coefficient c: capacitor r: resistance from the equation above, c can be obtained based on f and k conditions of s1c60n02. if the c value is smaller within the conditions, the precision is higher. if the c value is determined by the above equation, the frequency (f cr1 ) by the standard resistance can be obtained by the following equation: f cr1 (khz) = k cr 1 thermistor 103at usage example at 25 c, the 103at resistance is 10 k ? . thus the standard resistance is 10 k ? . the f and k conditions of s1c60n02 are as follows: f(max) = 85 khz (limit of ic operation) 1 k 3 (oscillation coefficient in s1c60n02) with these conditions, the following equation can be derived: 85 khz k cr 2(tmax) r 2(tmax) : minimum resistance of thermistor k=3 is the worst condition, then c 3 85 10 3 2.23 10 3 = 15,800 (pf) as a result, the following is determined: c = 22,000 (pf) (value for general purpose product) the following is obtained: f cr1 = (1 to 3) 22,000 10 -12 10 10 3 = 4.5 to 13.5 (khz) by the above equations, the capacitor value (22,000 pf) and the oscillation frequency (4.5?3.5 khz) by the standard resistance are determined. for the details of 103at, see appendix c.
82 epson s1c60n02 technical manual appendix: technical information setting up counter initial value the capacitor value and the oscillation frequency by the standard resistance are determined in the previous section. this section describes how to set the initial value of the a/d converter's up counter. for a/d converter principals, see the technical manual for the s1c60n02. fx'tal: f cr1 : f cr2 : 65535 - c upi : c ups : 65535: t a : crystal oscillation frequency standard oscillation frequency thermistor oscillation frequency up counter initial value thermistor count value max. counter value count time 65535 0 65535 - c upi c ups f cr1 t a f cr2 t a up counter ? ? ? ? figure a.2 shows the relationship between the up counter and the up-down counter. the following conditions should be satisfied: condition (a): the up-down counter should not overflow during an up-count condition (b): the up counter should not overflow during a down- count with these conditions, the up counter initial value can be obtained with the following equations: table a.2 item obtain the up counter initial value from the condition (a) obtain the up counter initial value from the condition (b) description from the condition (a) the following equation is derived: 65535 > t a ?x'tal = 65535 - c upi f cr1 fx'tal c upi > ( 1- f cr1 fx'tal ) 65535 initial value 65535 - c upi ...(a) from the condition (b) the following equation is derived: 65535 > c ups = t a f cr2 = f cr2 f cr1 (65535 - c upi ) c upi = ( 1 - f cr1 f cr2 ) 65535 initial value 65535 - c upi ...(b) from the above equations (a) and (b) the initial value can be determined. thermistor 103at usage example from fx'tal = 65 khz, f cr1 = 4.5?3.5 khz c upi = ( 1 - 4.5 10 3 65 10 3 ) 65535 59571 c upi = ( 1 - 13.5 10 3 65 10 3 ) 65535 50707 initial value 65535 - 59571 = 5964 ...(a)' f cr1 = 4.5?3.5 khz, f cr2 = 85 khz (ic operational maximum) c upi = ( 1 - 4.5 10 3 85 10 3 ) 65535 60608 c upi = ( 1 - 13.5 10 3 85 10 3 ) 65535 53837 initial value 65535 - 60608 = 4927 ...(b)' from (a)' and (b)', the initial value should be set less than 4927. here, it is set to 3000. (under the conditions, if the initial value is smaller, the precision is higher.) the initial value (3,000) for the up counter is derived from the above equations.
s1c60n02 technical manual epson 83 appendix: technical information computation method of displayed temperature by linear approximation the following shows the linear approximation equation to derive the displayed temperature. displayed temperature ( c) = (count after a/d conversion - count for minimum in the temperature range) this equation derives the displayed temperature. the following shows the method. first, each value is described. [count value after a/d conversion] this is the up counter value after an a/d conversion. [count for the minimum value of the temperature range] [minimum value of the temperature range] to derive the displayed temperature by the linear approximation, the temperature range must be determined for the linear approxi- mation. in this example, the measured temperature range is -30 to 70?. if the temperature range for the linear approximation is set for every 10?, the temperature range is -30 to -20?, -20 to -10?, and so on. the smallest value of each temperature range segment is the minimum value of the temperature range. the largest value is the maximum value of the temperature range. the count value for the minimum value for the temperature range is expressed by the following equation: a/d converter count value = f cr2 by substituting r 2 (thermistor resistance), r 1 (standard resist- ance), and the up counter initial value with actual values, the count value for the minimum of the temperature range is obtained. [linear approximation coefficient] the linear approximation coefficient is the value that shows how many degrees (centigrade) for one count in the temperature range. the linear approximation coefficient is expressed by the following equation: linear approximation coefficient = temperature range count for max. of temperature range - count for min. of temperature range (as you can see, the temperature range is smaller, the precision is higher.)
84 epson s1c60n02 technical manual appendix: technical information the following table shows the various values for every 10?. table a.3 temperature ( ? the following example derives a displayed temperature using the values in the above table. example: assume the count value after an a/d conversion is 3200. then, it is between 3608 and 2481 in the table. as a result the tempera- ture range is 20?to 30?. the count value for the minimum value of the temperature range: 2481 the count value for the maximum value of the temperature range: 3608 then, the linear approximation coefficient of the temperature range is 0.00887. as a result, the displayed temperature is derived as follows: displayed temperature = (3200 - 2481) c) = 26.377 ( c)
s1c60n02 technical manual epson 85 appendix: technical information appendix b error factors when a temperature is computed using the s1c60n02 a/d con- verter and the thermistor, the following error factors should be taken in account: thermistor resistance dispersion the thermistor manufacturer should guarantee the precision. a/d converter error factors error (circuit) by a/d conversion in r 1 (standard resistance) and r 2 (thermistor) by the cr oscillation at the standard resistor (r 1 ), the up counter and the up-down counter increment the counter with the timing shown below. fig. b.1 adrun register cs pin adout output up counter enable up counter (c0) clock (up-down counter) up-down counter enable up-down counter (tc0) starts counting starts counting after the a/d run, the first trailing edge of the cs pin triggers the up counter enable. from the next trailing edge, the up counter starts to count. in addition, the first trailing edge of the clock after the up counter is enabled, the up-down counter is enabled and it starts to count from the next trailing edge. when the up counter value becomes 0, the up counter is disabled. the next trailing edge of the clock disables the up-down counter. if this situation occurs, the error described below will result. started: min. the same is true in the cr oscillation by thermistor r 2 , and a similar error occurs. exception: because the up-down counter is down-counted the following counting error occurs: started: min. therefore, as for the error from the circuit, a maximum of 2 count errors results.
86 epson s1c60n02 technical manual appendix: technical information the effect of the maximum 2 count error is given below. ? ? ? ? in addition, the number of counts of the up-down counter should be the same. then the following equation is true: f clk then, from (3), assume the up-down counter counts shifted 2 counts, the following equations are true: f clk (1) is the count error at the cr oscillation by the standard resistor. (2) is the count error at the cr oscillation by thermistor. the total error is expressed by the equation (3)' with the ratio of f cr1 and f cr2 . the segment that represents the error in the equation (3)' is 2 (f cr2 /f clk ). if the values c upi1 and c ups are large, this error factor may be ignored. for how to determine the initial value (c upi1 ) of the up counter, see the section describing thermometer design steps. cr oscillation constant (k) error the constant, k, is determined by the logic level of the internal schmidt trigger of the ic. however, in s1c60n02, the schmidt trigger shares the circuit with the standard resistor and thermis- tor. as a result, oscillation is canceled and no error occurs. error by transistor on resistance the transistor on resistance is directly connected to the standard resistor and thermistor; this may cause an error. see the circuit shown next to figure b.2 below. in this circuit, the capacitor is charged by tr1, t2 on and tr3 off. if the voltage at the cs pin changes to a certain level, the capacitor charge is drained by tr1, tr2 off and tr3 on. as a result, the cr oscilla- tion is generated as in figure b.3.
s1c60n02 technical manual epson 87 appendix: technical information at this time, if the on resistance of tr1 and tr2 on is t1 and the on resistance of tr3 is t2, the constance may be effected. the s1c60n02 transistors are standardized to have a maximum of 100 ? . this standard includes dispersion by temperature characteristics, pch and nch. the evaluation board transistor uses standard ics and the actual resistance is about 1 k ? . (this is not guaranteed and should be regarded as just a reference.) the error by on resistance of this transistor is expressed by the following equations: ? ? ? ? ?
88 epson s1c60n02 technical manual appendix: technical information transistor on resistance error when thermistor 103at measures 60? ? 3 = { 1 - 10 10 3 } 100 1% (10 10 3 + 100) ? 4 = { 1 - 3.217 10 3 } 100 3% (3.217 10 3 + 100) as a result, the following errors occur by directly connecting the transistor on resistance: 1% at cr oscillation on the standard resistor 3% at cr oscillation on thermistor the transistor on resistance effect is smaller if r 1 and r 2 are larger. (see equation ? 3 and ? 4 .) in the high temperature range, the r 2 value becomes small and ? 4 becomes large. this causes precision degradation. compensation is needed to implement a user's required precision. figure b.4 shows the a/d converter on resistance errors ( ? 4 - ? 3 ) of the evaluation board and the actual ic when the thermistor 103at is used. on resistance errors when thermistor 103at is used example: fig. b.4 30 20 10 0 -10 -20 -50 -20 0 25 50 70 100 error ? 4 - ? 3 (%) te mperature ( c) error by on resistance (1 k ? ) in the evaluation board error by on resistance (100 ? ) in the actual ic this figure shows the plot of errors when the on resistance in the evaluation board is 1 k ? and that of the actual ic is 100 ? . as shown in the figure, the evaluation board's error is larger than the actual ic, therefore, programs evaluated using the evaluation board may not operate normally in the actual ic. to avoid this problem, it is necessary to reduce the on resistance error. choose a thermistor resistance as large as possible to reduce the on resistance error. at least 10 k ? (ta = 25?) of resistance is required. the plot (figure b.4) is in this case shows a 10 k ? thermistor resistance that satisfies the minimum resistance condition, note, however, that there is a large error increase in temperature over 60?.
s1c60n02 technical manual epson 89 appendix: technical information error by floating capacity the floating capacity of the inside of an ic, board, lead of a sensor and others may be an error factor. floating capacity inside an ic may be several pf and it may be ignored by increasing the capaci- tor value. software error in the software, it is normal to convert the counter value to an actual temperature by a linear approximation. in this method, an error may be caused by the linear approximation in the tempera- ture measured range. as shown in figure b.5 below, if the temperature range measured is 20? to 30?, the weight of 1 count differs between 20? and 29?. fig. b.5 30 (1) (2) temperature ( c) counts (times) 29 20 on the slope (1), the linear approximation coefficient in this seg- ment for 1 count is large, and the slope (2) has a smaller coeffi- cient. for example, if this segment (20? to 30?) is calculated by the same linear approximation coefficient, and if the 20? is the reference point, then, at 29?, the linear approximation coefficient becomes the largest and, at 29?, the error is maximum. the error may differ depending on the temperature measured by the software, up counter initial value and thermistor type. for example, when using a 10 k ? (ta = 25?) thermistor for the actual ic, the on resistance in the evaluation board can be close to that of the actual ic by connecting 10 thermistors in series to configure a 100 k ? (ta = 25?) thermistor and by using a 100 k ? reference resistance and reducing the capacitance to 1/10. however, on resistance is so susceptible to source voltage levels and board mount conditions affect the conversion results, there- fore, it is impossible to obtain exactly the same results between the evaluation board and the actual ic even if the methods described above are used. it is necessary to evaluate the a/d conversion using the results of several samples from the final product.
90 epson s1c60n02 technical manual appendix: technical information at thermistor high precision thermistor appendix c features the at thermistor has a high precision thermistor with small resistance and b constant error margin. using the at thermistor as a temperature sensor does not require adjustment between a control circuit and the sensor; and the at thermistor provides a temperature precision of ?.3?. as a result, a high precision temperature control and temperature display are possible. error margins of resistance and temperature characteristics are very small. small age-based change and high reliability low price high durability usage air conditioners, fan heaters, ff heaters, refrigerators, water heaters, boiler/kitchen appliances, copiers, printers, facsimiles, automatic vending machines, agricultural equipment, automobiles (for external temperature, internal temperature, air flow sensor), portable thermometers, medical equipment, thermos-type contain- ers, solar heating system, automatic toilet seats, fire alarms, home automation type number 103 at - 2 external type high precision at thermistor zero load resistance (25?) 103: 10 k ? resistance margin graph temperature precision graph -40 1 2 3 4 5 -30 -20 -10 0 10 20 30 4 05060708090100 ambient temperature ( c) resistance margin ( %) -40 0.5 1.0 1.5 2.0 2.5 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 0.5 c 0.7 c 1 c ambient temperature ( c) temperature margin ( c)
s1c60n02 technical manual epson 91 appendix: technical information comparison between at type and others ratings thermistor at type other type r 25 margin 1% 5% b margin 1% 3% temperature margine (25 c) 0.3 c 1.3 c temperature control (display) for every 1 c circuit adhustment - not required circuit adjystment - required type 102at-1 202at-1 502at-1 103at-1 102at-2 202at-2 502at-2 103at-2, 3 203at-2 103at-4 r 25 1 k ? 1% 2 k ? 1% 5 k ? 1% 10 k ? 1% 1 k ? 1% 2 k ? 1% 5 k ? 1% 10 k ? 1% 20 k ? 1% 10 k ? 1% b constant 3100k 1% 3182k 1% 3324k 1% 3435k 1% 3100k 1% 3182k 1% 3324k 1% 3435k 1% 4013k 1% 3435k 1% thermal radiation constant (mw/ c) approx. 3 approx. 3 approx. 3 approx. 3 approx. 2 approx. 2 approx. 2 approx. 2 approx. 2 approx. 2 thermal constant (s) approx. 75 approx. 75 approx. 75 approx. 75 approx. 15 approx. 15 approx. 15 approx. 15 approx. 15 approx. 10 maximum power (mw) at 25 c 15 15 15 15 10 10 10 10 10 10 temperature range ( c) -50 to 90 -50 to 90 -50 to 105 -50 to 105 -50 to 90 -50 to 90 -50 to 110 -50 to 110 -50 to 110 -30 to 90 external dimension (at-3, 4 in omission) 103at at-1 at-2 max. 15 max. 5 600 5 1 max.3.5 max.2.4 2.54 0.25 0.7 max.4.0 8.5 1 17 1.5 +20 ? printed taper cut color code epoxy resin 0.5 tinned 42 alloy color code : black : red : yellow : white : no color : type 102at-2 202at-2 502at-2 103at-2 203at-2 soldered thermistor tpe resin tpe resin covered parallel line 0.18 12 core (0.3sq) black thermal response 20 40 60 63.2 95.0 86.5 100 0102 030405060708090100 time (s) temperature difference (%) at-2 (in the air) at-1 (in the air) board soldering method 8.5 board proper usage example proper soldering conditions: 260 c, 10 seconds or less 2.54
92 epson s1c60n02 technical manual appendix: technical information resistance - temperature characteristics -50 to 29? 30 to110? temp ( c) -50 -49 -48 -47 -46 -45 -44 -43 -42 -41 -40 -39 -38 -37 -36 -35 -34 -33 -32 -31 -30 -29 -28 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 rmax (k ? ) 344.4 324.7 306.4 289.2 273.2 258.1 244.0 230.8 218.5 206.8 195.9 185.4 175.5 166.2 157.5 149.3 141.6 134.4 127.6 121.2 115.1 109.3 103.8 98.63 93.75 89.15 84.82 80.72 76.85 73.20 69.74 66.42 63.27 60.30 57.49 54.83 52.31 49.93 47.67 45.53 43.50 41.54 39.68 37.91 36.24 34.65 33.14 31.71 30.35 29.06 27.83 26.64 25.51 24.44 23.42 22.45 21.52 20.64 19.80 19.00 18.24 17.51 16.80 16.13 15.50 14.89 14.31 13.75 13.22 12.72 12.23 11.77 11.32 10.90 10.49 10.10 9.732 9.381 9.044 8.721 rst (k ? ) 329.2 310.7 293.3 277.0 261.8 247.5 234.1 221.6 209.8 198.7 188.4 178.3 168.9 160.1 151.8 144.0 136.6 129.7 123.2 117.1 111.3 105.7 100.4 95.47 90.80 86.39 82.22 78.29 74.58 71.07 67.74 64.54 61.52 58.66 55.95 53.39 50.96 48.66 46.48 44.41 42.45 40.56 38.76 37.05 35.43 33.89 32.43 31.04 29.72 28.47 27.28 26.13 25.03 23.99 22.99 22.05 21.15 20.29 19.48 18.70 17.96 17.24 16.55 15.90 15.28 14.68 14.12 13.57 13.06 12.56 12.09 11.63 11.20 10.78 10.38 10.00 9.632 9.281 8.944 8.622 rmin (k ? ) 314.7 297.2 280.7 265.3 250.8 237.3 224.6 212.7 201.5 191.0 181.1 171.5 162.6 154.2 146.2 138.8 131.8 125.2 118.9 113.1 107.5 102.2 97.16 92.41 87.93 83.70 79.71 75.93 72.36 68.99 65.80 62.72 59.81 57.05 54.44 51.97 49.63 47.42 45.31 43.32 41.43 39.59 37.85 36.20 34.63 33.14 31.73 30.39 29.11 27.89 26.74 25.62 24.55 23.54 22.57 21.66 20.78 19.95 19.15 18.40 17.67 16.97 16.31 15.67 15.06 14.48 13.93 13.40 12.89 12.41 11.95 11.50 11.07 10.66 10.27 9.900 9.533 9.181 8.845 8.523 103at temp ( c) 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 rmax (k ? ) 8.412 8.113 7.826 7.551 7.288 7.036 6.793 6.561 6.338 6.124 5.918 5.719 5.527 5.343 5.166 4.996 4.833 4.676 4.525 4.380 4.240 4.104 3.973 3.847 3.726 3.609 3.497 3.389 3.285 3.184 3.088 2.994 2.903 2.816 2.732 2.650 2.572 2.496 2.423 2.353 2.285 2.219 2.155 2.093 2.034 1.976 1.920 1.866 1.814 1.764 1.716 1.668 1.623 1.578 1.536 1.494 4.454 1.415 1.378 1.341 1.306 1.271 1.238 1.206 1.175 1.144 1.115 1.087 1.059 1.032 1.006 0.9812 0.9567 0.9330 0.9100 0.8877 0.8660 0.8456 0.8245 0.8047 rst (k ? ) 8.313 8.015 7.729 7.455 7.192 6.941 6.699 6.468 6.246 6.033 5.828 5.630 5.439 5.256 5.080 4.912 4.749 4.594 4.444 4.300 4.161 4.026 3.897 3.772 3.652 3.537 3.426 3.319 3.216 3.116 3.021 2.928 2.838 2.752 2.669 2.589 2.512 2.437 2.365 2.296 2.229 2.163 2.101 2.040 1.981 1.924 1.870 1.817 1.766 1.716 1.669 1.622 1.577 1.534 1.492 1.451 1.412 1.374 1.337 1.301 1.266 1.233 1.200 1.169 1.138 1.108 1.080 1.052 1.025 0.9988 0.9735 0.9489 0.9250 0.9018 0.8793 0.8575 0.8364 0.8159 0.7960 0.7767 rmin (k ? ) 8.215 7.917 7.632 7.359 7.097 6.846 6.606 6.375 6.154 5.942 5.739 5.541 5.352 5.170 4.996 4.828 4.667 4.512 4.364 4.221 4.084 3.950 3.822 3.698 3.579 3.465 3.355 3.249 3.148 3.049 2.955 2.863 2.775 2.690 2.608 2.529 2.452 2.379 2.308 2.240 2.174 2.109 2.047 1.987 1.930 1.874 1.820 1.768 1.718 1.669 1.622 1.577 1.533 1.490 1.449 1.409 1.371 1.333 1.297 1.262 1.228 1.195 1.163 1.132 1.102 1.073 1.045 1.018 0.9918 0.9663 0.9416 0.9175 0.8942 0.8716 0.8496 0.8284 0.8077 0.7877 0.7683 0.7495 103at
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m l epson electronic devices website electronic devices marketing division http://www.epsondevice.com t echnical manual s1c60n02 first issue august, 1997 printed january, 2004 in japan a document code: 404572204

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